Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	15682298	1		T1	300		T2	5		T3	5
full_word	16378776	1		T1	5225		T2	5		T3	5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32060774	1		T1	5525		T2	10		T3	10
auto[TlIntgErrCmd]	107	1		T193	1		T226	6		T227	6
auto[TlIntgErrData]	98	1		T193	5		T226	2		T227	1
auto[TlIntgErrBoth]	95	1		T193	4		T226	2		T227	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31539106	1		T1	3000		T2	2		T3	2
auto[1]	521968	1		T1	2525		T2	8		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15545556	1		T1	124		T3	2		T36	1
auto[TlIntgErrNone]	partial	auto[1]	136467	1		T1	176		T2	5		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	15993399	1		T1	2876		T2	2		T36	1
auto[TlIntgErrNone]	full_word	auto[1]	385352	1		T1	2349		T2	3		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T226	2		T227	3		T245	4
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T226	4		T227	3		T245	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T245	1		T299	1		T304	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T193	1		T299	2		T305	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T193	3		T227	1		T245	2
auto[TlIntgErrData]	partial	auto[1]	43	1		T193	2		T226	2		T245	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T245	2		T302	2		T300	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T306	1		T307	1		T308	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1		T193	2		T227	2		T245	4
auto[TlIntgErrBoth]	partial	auto[1]	39	1		T193	1		T226	2		T227	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T309	1		T302	1		T304	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T193	1		T310	1		T311	1