Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	498841381	12395	0	0
ep_in_enable_rd_A	498841381	3069	0	0
ep_out_enable_rd_A	498841381	3664	0	0
in_iso_rd_A	498841381	3139	0	0
intr_enable_rd_A	498841381	4653	0	0
out_iso_rd_A	498841381	3693	0	0
phy_config_rd_A	498841381	1966	0	0
phy_pins_drive_rd_A	498841381	2801	0	0
rxenable_setup_rd_A	498841381	3162	0	0
set_nak_out_rd_A	498841381	3412	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498841381	12395	0	0
T193	16694	1	0	0
T194	4053	6	0	0
T195	5495	692	0	0
T221	3547	390	0	0
T222	9564	321	0	0
T226	23352	4	0	0
T227	12610	4	0	0
T230	4269	10	0	0
T237	4827	8	0	0
T244	4368	11	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498841381	3069	0	0
T226	23352	258	0	0
T237	4827	3	0	0
T258	6125	2	0	0
T260	10148	79	0	0
T271	5992	7	0	0
T273	6497	30	0	0
T274	5726	3	0	0
T275	5446	11	0	0
T278	10633	19	0	0
T279	9324	1	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498841381	3664	0	0
T226	23352	390	0	0
T237	4827	8	0	0
T258	6125	40	0	0
T260	10148	86	0	0
T271	5992	16	0	0
T273	6497	10	0	0
T274	5726	7	0	0
T275	5446	48	0	0
T278	10633	20	0	0
T279	9324	2	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498841381	3139	0	0
T226	23352	306	0	0
T237	4827	7	0	0
T258	6125	43	0	0
T260	10148	72	0	0
T264	20114	172	0	0
T271	5992	7	0	0
T273	6497	28	0	0
T274	5726	7	0	0
T275	5446	2	0	0
T279	9324	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498841381	4653	0	0
T204	3225	27	0	0
T226	23352	319	0	0
T237	4827	14	0	0
T258	6125	70	0	0
T271	5992	33	0	0
T273	6497	39	0	0
T274	5726	2	0	0
T275	5446	58	0	0
T280	1763	3	0	0
T281	1834	25	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498841381	3693	0	0
T226	23352	322	0	0
T237	4827	7	0	0
T258	6125	2	0	0
T260	10148	82	0	0
T271	5992	4	0	0
T273	6497	33	0	0
T274	5726	4	0	0
T275	5446	7	0	0
T278	10633	19	0	0
T279	9324	27	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498841381	1966	0	0
T226	23352	200	0	0
T237	4827	22	0	0
T258	6125	17	0	0
T260	10148	68	0	0
T264	20114	172	0	0
T271	5992	8	0	0
T274	5726	3	0	0
T275	5446	10	0	0
T278	10633	27	0	0
T279	9324	21	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498841381	2801	0	0
T226	23352	199	0	0
T237	4827	48	0	0
T258	6125	4	0	0
T260	10148	74	0	0
T271	5992	45	0	0
T273	6497	24	0	0
T274	5726	10	0	0
T275	5446	41	0	0
T278	10633	18	0	0
T279	9324	11	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498841381	3162	0	0
T226	23352	256	0	0
T237	4827	48	0	0
T258	6125	2	0	0
T260	10148	85	0	0
T271	5992	22	0	0
T273	6497	39	0	0
T274	5726	15	0	0
T275	5446	8	0	0
T278	10633	12	0	0
T279	9324	38	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498841381	3412	0	0
T222	9564	3	0	0
T226	23352	191	0	0
T231	7861	1	0	0
T237	4827	49	0	0
T258	6125	38	0	0
T260	10148	94	0	0
T271	5992	35	0	0
T273	6497	25	0	0
T275	5446	36	0	0
T278	10633	34	0	0