Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_ram_1p_adv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_no_stubbed_memory.u_memory_1p 100.00 100.00 100.00 100.00



Module Instance : tb.dut.gen_no_stubbed_memory.u_memory_1p

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 97.06 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.03 97.53 88.06 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_mem 95.24 85.71 100.00 100.00
u_req_d_buf 100.00 100.00
u_write_d_buf 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_ram_1p_adv
Line No.TotalCoveredPercent
TOTAL2323100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN12311100.00
ALWAYS12633100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13800
CONT_ASSIGN14711100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN24800
CONT_ASSIGN24911100.00
CONT_ASSIGN25111100.00
CONT_ASSIGN25511100.00
CONT_ASSIGN31011100.00
CONT_ASSIGN31111100.00
CONT_ASSIGN31211100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31400
CONT_ASSIGN35311100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35600
CONT_ASSIGN35911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 1 1
103 1 1
123 1 1
126 1 1
127 1 1
129 1 1
133 1 1
134 1 1
135 1 1
136 1 1
137 1 1
138 unreachable
147 1 1
156 1 1
248 unreachable
249 1 1
251 1 1
255 1 1
310 1 1
311 1 1
312 1 1
313 1 1
314 unreachable
353 1 1
354 1 1
356 unreachable
359 1 1


Branch Coverage for Module : prim_ram_1p_adv
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 126 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 126 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_ram_1p_adv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CannotHaveEccAndParity_A 2634 2634 0 0


CannotHaveEccAndParity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2634 2634 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T28 1 1 0 0
T29 1 1 0 0
T36 1 1 0 0
T37 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%