Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14717598	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	15512462	1		T1	19		T2	9		T3	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29600254	1		T1	61		T2	2		T3	2
values[0x0]	314072	1		T1	19		T2	7		T3	5
values[0x1]	315734	1		T1	6		T2	2		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11731566	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	18498494	1		T1	44		T2	9		T3	5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	81109	1		T31	5		T4	97		T5	340
valid_sources[0x01]	293718	1		T31	3		T7	1		T4	103
valid_sources[0x02]	82219	1		T31	7		T7	1		T4	82
valid_sources[0x03]	120628	1		T31	5		T7	1		T4	82
valid_sources[0x04]	83168	1		T1	2		T31	1		T7	2
valid_sources[0x05]	82358	1		T1	2		T31	6		T29	1
valid_sources[0x06]	327024	1		T26	2		T31	3		T32	1
valid_sources[0x07]	319888	1		T31	4		T32	1		T7	2
valid_sources[0x08]	154630	1		T28	1		T7	3		T4	92
valid_sources[0x09]	104797	1		T31	2		T4	69		T5	298
valid_sources[0x0a]	81323	1		T31	3		T7	1		T4	90
valid_sources[0x0b]	82346	1		T31	2		T4	65		T5	309
valid_sources[0x0c]	109845	1		T3	1		T31	4		T4	94
valid_sources[0x0d]	81896	1		T26	1		T31	5		T4	82
valid_sources[0x0e]	82366	1		T31	4		T4	63		T5	323
valid_sources[0x0f]	124949	1		T31	5		T7	1		T4	73
valid_sources[0x10]	82223	1		T31	2		T4	82		T5	306
valid_sources[0x11]	81525	1		T31	2		T7	3		T4	83
valid_sources[0x12]	80954	1		T31	5		T4	79		T5	327
valid_sources[0x13]	82129	1		T26	1		T31	2		T17	10
valid_sources[0x14]	152411	1		T31	3		T7	2		T4	73
valid_sources[0x15]	82574	1		T1	1		T31	3		T7	1
valid_sources[0x16]	81948	1		T1	2		T31	7		T7	10
valid_sources[0x17]	183232	1		T31	4		T7	2		T4	68
valid_sources[0x18]	203269	1		T1	1		T31	5		T7	1
valid_sources[0x19]	82219	1		T1	2		T31	5		T32	1
valid_sources[0x1a]	82345	1		T31	9		T4	64		T5	284
valid_sources[0x1b]	82995	1		T31	3		T4	92		T5	289
valid_sources[0x1c]	86194	1		T31	4		T4	82		T19	4
valid_sources[0x1d]	248663	1		T31	9		T4	107		T5	295
valid_sources[0x1e]	154742	1		T31	4		T7	5		T4	76
valid_sources[0x1f]	84244	1		T31	10		T7	1		T4	89
valid_sources[0x20]	82057	1		T26	1		T31	3		T7	5
valid_sources[0x21]	81040	1		T31	4		T4	62		T5	281
valid_sources[0x22]	81669	1		T1	2		T3	1		T31	7
valid_sources[0x23]	111918	1		T1	4		T31	1		T29	2
valid_sources[0x24]	81621	1		T31	1		T4	59		T5	295
valid_sources[0x25]	81408	1		T1	1		T3	1		T31	7
valid_sources[0x26]	112908	1		T31	3		T7	1		T4	65
valid_sources[0x27]	82853	1		T1	2		T31	4		T7	1
valid_sources[0x28]	81343	1		T31	3		T4	78		T5	315
valid_sources[0x29]	202027	1		T1	2		T31	7		T4	85
valid_sources[0x2a]	82219	1		T31	2		T4	106		T5	297
valid_sources[0x2b]	202037	1		T27	1		T31	2		T4	80
valid_sources[0x2c]	121197	1		T30	1		T31	2		T4	81
valid_sources[0x2d]	81603	1		T1	2		T25	14		T31	1
valid_sources[0x2e]	103608	1		T1	1		T31	7		T4	62
valid_sources[0x2f]	104601	1		T31	1		T4	81		T5	300
valid_sources[0x30]	197344	1		T1	1		T31	6		T8	98
valid_sources[0x31]	81937	1		T31	7		T4	88		T5	346
valid_sources[0x32]	82320	1		T31	5		T7	2		T18	1
valid_sources[0x33]	134210	1		T31	4		T18	1		T4	100
valid_sources[0x34]	83835	1		T2	1		T31	5		T4	105
valid_sources[0x35]	162343	1		T31	3		T4	74		T5	338
valid_sources[0x36]	84014	1		T31	4		T32	1		T7	1
valid_sources[0x37]	81561	1		T31	7		T29	1		T7	1
valid_sources[0x38]	185410	1		T31	6		T7	1		T4	84
valid_sources[0x39]	81527	1		T28	1		T31	1		T4	95
valid_sources[0x3a]	82758	1		T31	3		T7	7		T4	117
valid_sources[0x3b]	83361	1		T31	3		T4	78		T5	313
valid_sources[0x3c]	131533	1		T30	1		T31	3		T29	1
valid_sources[0x3d]	82530	1		T31	2		T4	105		T5	347
valid_sources[0x3e]	82665	1		T31	6		T4	96		T5	295
valid_sources[0x3f]	82064	1		T31	1		T32	1		T4	84
valid_sources[0x40]	82017	1		T31	2		T7	2		T4	77
valid_sources[0x41]	86339	1		T31	1		T4	95		T19	103
valid_sources[0x42]	82654	1		T31	5		T4	104		T5	311
valid_sources[0x43]	83618	1		T31	3		T4	88		T5	287
valid_sources[0x44]	109611	1		T31	4		T7	1		T4	90
valid_sources[0x45]	82693	1		T31	2		T4	64		T5	310
valid_sources[0x46]	81967	1		T27	4		T31	1		T7	1
valid_sources[0x47]	121653	1		T31	6		T32	1		T4	99
valid_sources[0x48]	81426	1		T31	3		T17	17		T18	1
valid_sources[0x49]	83163	1		T31	3		T17	17		T4	92
valid_sources[0x4a]	110430	1		T31	4		T4	75		T5	287
valid_sources[0x4b]	111752	1		T31	6		T7	1		T4	66
valid_sources[0x4c]	82309	1		T31	6		T7	2		T4	105
valid_sources[0x4d]	81360	1		T31	5		T7	2		T4	112
valid_sources[0x4e]	81923	1		T1	1		T31	3		T7	4
valid_sources[0x4f]	86132	1		T31	1		T29	1		T7	7
valid_sources[0x50]	82382	1		T31	5		T29	1		T7	4
valid_sources[0x51]	83999	1		T31	2		T7	5		T4	80
valid_sources[0x52]	82201	1		T31	5		T7	3		T4	72
valid_sources[0x53]	85168	1		T31	7		T4	54		T5	280
valid_sources[0x54]	82260	1		T31	3		T7	4		T4	63
valid_sources[0x55]	81731	1		T31	5		T4	80		T5	300
valid_sources[0x56]	82577	1		T31	6		T4	88		T5	318
valid_sources[0x57]	316493	1		T31	1		T7	3		T4	72
valid_sources[0x58]	239469	1		T1	4		T31	3		T32	1
valid_sources[0x59]	81473	1		T3	2		T31	3		T4	85
valid_sources[0x5a]	149796	1		T1	1		T31	6		T4	110
valid_sources[0x5b]	192952	1		T31	11		T29	1		T4	83
valid_sources[0x5c]	82168	1		T31	3		T7	2		T4	75
valid_sources[0x5d]	81933	1		T31	4		T29	1		T7	6
valid_sources[0x5e]	83462	1		T27	2		T31	3		T4	99
valid_sources[0x5f]	83249	1		T31	4		T4	49		T5	316
valid_sources[0x60]	113452	1		T31	1		T7	1		T4	82
valid_sources[0x61]	309708	1		T27	2		T31	4		T18	1
valid_sources[0x62]	81071	1		T31	4		T7	2		T4	86
valid_sources[0x63]	84208	1		T31	3		T4	116		T5	288
valid_sources[0x64]	82526	1		T31	2		T4	86		T5	341
valid_sources[0x65]	82852	1		T31	2		T4	105		T5	306
valid_sources[0x66]	81806	1		T31	2		T18	1		T4	101
valid_sources[0x67]	82097	1		T1	3		T31	3		T4	91
valid_sources[0x68]	180168	1		T31	7		T4	72		T5	287
valid_sources[0x69]	82095	1		T31	6		T4	71		T5	259
valid_sources[0x6a]	82067	1		T31	3		T4	79		T5	309
valid_sources[0x6b]	83903	1		T31	1		T4	84		T5	300
valid_sources[0x6c]	173350	1		T1	1		T26	1		T31	3
valid_sources[0x6d]	183010	1		T31	7		T7	3		T4	76
valid_sources[0x6e]	116923	1		T30	2		T31	5		T4	60
valid_sources[0x6f]	201440	1		T31	2		T4	93		T5	291
valid_sources[0x70]	82197	1		T31	1		T4	72		T5	344
valid_sources[0x71]	81787	1		T31	4		T7	4		T4	83
valid_sources[0x72]	81792	1		T31	2		T4	59		T5	290
valid_sources[0x73]	86805	1		T31	3		T4	114		T5	315
valid_sources[0x74]	81126	1		T31	3		T4	102		T5	266
valid_sources[0x75]	82798	1		T1	1		T31	1		T4	98
valid_sources[0x76]	275659	1		T1	1		T31	3		T7	4
valid_sources[0x77]	82577	1		T1	1		T31	4		T4	126
valid_sources[0x78]	81492	1		T1	1		T31	5		T7	4
valid_sources[0x79]	81467	1		T1	1		T31	4		T7	2
valid_sources[0x7a]	83119	1		T1	2		T31	4		T29	1
valid_sources[0x7b]	81068	1		T31	6		T7	2		T4	97
valid_sources[0x7c]	80947	1		T28	1		T31	2		T4	80
valid_sources[0x7d]	130264	1		T31	3		T4	61		T5	306
valid_sources[0x7e]	81801	1		T31	3		T4	93		T5	303
valid_sources[0x7f]	82964	1		T1	5		T31	2		T29	1
valid_sources[0x80]	84277	1		T31	1		T7	1		T4	111

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15007204

1

T1

3

T2

2

T3

1

values[0x0]

all_enables

biggest_size

260081

1

T1

13

T2

6

T3

2

values[0x1]

all_enables

biggest_size

245177

1

T1

3

T2

1

T3

1