Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14733188	1		T1	67		T2	2		T3	6
full_word	15513572	1		T1	19		T2	9		T3	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30246460	1		T1	86		T2	11		T3	10
auto[TlIntgErrCmd]	106	1		T198	9		T220	8		T225	2
auto[TlIntgErrData]	99	1		T198	3		T220	5		T225	7
auto[TlIntgErrBoth]	95	1		T198	8		T220	7		T225	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29602434	1		T1	61		T2	2		T3	2
auto[1]	644326	1		T1	25		T2	9		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14594845	1		T1	58		T3	1		T30	2
auto[TlIntgErrNone]	partial	auto[1]	138064	1		T1	9		T2	2		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	15007439	1		T1	3		T2	2		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	506112	1		T1	16		T2	7		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	45	1		T198	7		T220	5		T225	2
auto[TlIntgErrCmd]	partial	auto[1]	52	1		T198	2		T220	2		T240	7
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T238	1		T301	1		T302	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T220	1		T303	2		T304	1
auto[TlIntgErrData]	partial	auto[0]	52	1		T198	2		T225	5		T240	3
auto[TlIntgErrData]	partial	auto[1]	41	1		T198	1		T220	5		T225	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T240	1		T300	1		T285	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T305	2		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	44	1		T198	5		T220	1		T240	2
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T198	3		T220	6		T225	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T298	1		T306	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T300	1		T303	1		T279	1