Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	506885191	11725	0	0
ep_in_enable_rd_A	506885191	2617	0	0
ep_out_enable_rd_A	506885191	2455	0	0
in_iso_rd_A	506885191	2625	0	0
intr_enable_rd_A	506885191	4081	0	0
out_iso_rd_A	506885191	2478	0	0
phy_config_rd_A	506885191	1731	0	0
phy_pins_drive_rd_A	506885191	2334	0	0
rxenable_setup_rd_A	506885191	2793	0	0
set_nak_out_rd_A	506885191	2524	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506885191	11725	0	0
T194	9208	12	0	0
T195	6446	293	0	0
T196	5265	8	0	0
T198	29522	8	0	0
T220	47894	1	0	0
T224	7547	880	0	0
T225	18938	4	0	0
T228	4573	953	0	0
T232	9282	9	0	0
T240	39464	4	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506885191	2617	0	0
T221	6836	9	0	0
T237	8346	6	0	0
T249	9025	105	0	0
T252	47320	231	0	0
T257	4774	79	0	0
T267	5096	33	0	0
T277	21850	28	0	0
T278	11424	21	0	0
T279	41867	433	0	0
T280	5794	1	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506885191	2455	0	0
T221	6836	74	0	0
T237	8346	7	0	0
T249	9025	91	0	0
T252	47320	229	0	0
T257	4774	6	0	0
T267	5096	12	0	0
T277	21850	3	0	0
T278	11424	48	0	0
T279	41867	379	0	0
T281	15407	2	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506885191	2625	0	0
T221	6836	50	0	0
T237	8346	11	0	0
T249	9025	94	0	0
T252	47320	243	0	0
T257	4774	108	0	0
T267	5096	30	0	0
T277	21850	31	0	0
T278	11424	50	0	0
T279	41867	433	0	0
T280	5794	17	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506885191	4081	0	0
T205	4824	8	0	0
T206	2896	12	0	0
T221	6836	39	0	0
T237	8346	5	0	0
T249	9025	82	0	0
T252	47320	219	0	0
T277	21850	12	0	0
T282	2453	25	0	0
T283	2193	28	0	0
T284	2809	17	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506885191	2478	0	0
T237	8346	50	0	0
T249	9025	83	0	0
T252	47320	211	0	0
T257	4774	65	0	0
T267	5096	41	0	0
T277	21850	22	0	0
T278	11424	67	0	0
T279	41867	410	0	0
T280	5794	26	0	0
T285	62479	498	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506885191	1731	0	0
T221	6836	22	0	0
T237	8346	16	0	0
T249	9025	72	0	0
T252	47320	186	0	0
T257	4774	12	0	0
T267	5096	15	0	0
T277	21850	14	0	0
T278	11424	31	0	0
T279	41867	231	0	0
T280	5794	7	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506885191	2334	0	0
T221	6836	2	0	0
T237	8346	32	0	0
T249	9025	77	0	0
T252	47320	246	0	0
T257	4774	72	0	0
T267	5096	22	0	0
T277	21850	16	0	0
T278	11424	44	0	0
T279	41867	443	0	0
T280	5794	22	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506885191	2793	0	0
T221	6836	41	0	0
T237	8346	39	0	0
T249	9025	69	0	0
T252	47320	179	0	0
T257	4774	46	0	0
T267	5096	6	0	0
T277	21850	37	0	0
T278	11424	17	0	0
T279	41867	512	0	0
T280	5794	20	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506885191	2524	0	0
T221	6836	1	0	0
T237	8346	4	0	0
T249	9025	59	0	0
T252	47320	231	0	0
T257	4774	37	0	0
T267	5096	27	0	0
T277	21850	27	0	0
T278	11424	112	0	0
T279	41867	519	0	0
T280	5794	36	0	0