Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usbdev_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.52 99.76 98.32 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 99.52 99.76 98.32 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.52 99.76 98.32 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.79 98.85 98.13 100.00 98.41 93.55


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.03 97.53 88.06 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test 100.00 100.00
u_avoutbuffer 100.00 100.00
u_avsetupbuffer 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_configin_0_buffer_0 100.00 100.00 100.00 100.00
u_configin_0_pend_0 100.00 100.00 100.00 100.00
u_configin_0_rdy_0 100.00 100.00 100.00 100.00
u_configin_0_sending_0 100.00 100.00 100.00 100.00
u_configin_0_size_0 100.00 100.00 100.00 100.00
u_configin_10_buffer_10 100.00 100.00 100.00 100.00
u_configin_10_pend_10 100.00 100.00 100.00 100.00
u_configin_10_rdy_10 100.00 100.00 100.00 100.00
u_configin_10_sending_10 100.00 100.00 100.00 100.00
u_configin_10_size_10 100.00 100.00 100.00 100.00
u_configin_11_buffer_11 100.00 100.00 100.00 100.00
u_configin_11_pend_11 100.00 100.00 100.00 100.00
u_configin_11_rdy_11 100.00 100.00 100.00 100.00
u_configin_11_sending_11 100.00 100.00 100.00 100.00
u_configin_11_size_11 100.00 100.00 100.00 100.00
u_configin_1_buffer_1 100.00 100.00 100.00 100.00
u_configin_1_pend_1 100.00 100.00 100.00 100.00
u_configin_1_rdy_1 100.00 100.00 100.00 100.00
u_configin_1_sending_1 100.00 100.00 100.00 100.00
u_configin_1_size_1 100.00 100.00 100.00 100.00
u_configin_2_buffer_2 100.00 100.00 100.00 100.00
u_configin_2_pend_2 100.00 100.00 100.00 100.00
u_configin_2_rdy_2 100.00 100.00 100.00 100.00
u_configin_2_sending_2 100.00 100.00 100.00 100.00
u_configin_2_size_2 100.00 100.00 100.00 100.00
u_configin_3_buffer_3 100.00 100.00 100.00 100.00
u_configin_3_pend_3 100.00 100.00 100.00 100.00
u_configin_3_rdy_3 100.00 100.00 100.00 100.00
u_configin_3_sending_3 100.00 100.00 100.00 100.00
u_configin_3_size_3 100.00 100.00 100.00 100.00
u_configin_4_buffer_4 100.00 100.00 100.00 100.00
u_configin_4_pend_4 100.00 100.00 100.00 100.00
u_configin_4_rdy_4 100.00 100.00 100.00 100.00
u_configin_4_sending_4 100.00 100.00 100.00 100.00
u_configin_4_size_4 100.00 100.00 100.00 100.00
u_configin_5_buffer_5 100.00 100.00 100.00 100.00
u_configin_5_pend_5 100.00 100.00 100.00 100.00
u_configin_5_rdy_5 100.00 100.00 100.00 100.00
u_configin_5_sending_5 100.00 100.00 100.00 100.00
u_configin_5_size_5 100.00 100.00 100.00 100.00
u_configin_6_buffer_6 100.00 100.00 100.00 100.00
u_configin_6_pend_6 100.00 100.00 100.00 100.00
u_configin_6_rdy_6 100.00 100.00 100.00 100.00
u_configin_6_sending_6 100.00 100.00 100.00 100.00
u_configin_6_size_6 100.00 100.00 100.00 100.00
u_configin_7_buffer_7 100.00 100.00 100.00 100.00
u_configin_7_pend_7 100.00 100.00 100.00 100.00
u_configin_7_rdy_7 100.00 100.00 100.00 100.00
u_configin_7_sending_7 100.00 100.00 100.00 100.00
u_configin_7_size_7 100.00 100.00 100.00 100.00
u_configin_8_buffer_8 100.00 100.00 100.00 100.00
u_configin_8_pend_8 100.00 100.00 100.00 100.00
u_configin_8_rdy_8 100.00 100.00 100.00 100.00
u_configin_8_sending_8 100.00 100.00 100.00 100.00
u_configin_8_size_8 100.00 100.00 100.00 100.00
u_configin_9_buffer_9 100.00 100.00 100.00 100.00
u_configin_9_pend_9 100.00 100.00 100.00 100.00
u_configin_9_rdy_9 100.00 100.00 100.00 100.00
u_configin_9_sending_9 100.00 100.00 100.00 100.00
u_configin_9_size_9 100.00 100.00 100.00 100.00
u_count_errors_bitstuff 100.00 100.00
u_count_errors_count 100.00 100.00
u_count_errors_crc16 100.00 100.00
u_count_errors_crc5 100.00 100.00
u_count_errors_pid_invalid 100.00 100.00
u_count_errors_rst 100.00 100.00
u_count_in_count 100.00 100.00
u_count_in_endpoints 100.00 100.00
u_count_in_nak 100.00 100.00
u_count_in_nodata 100.00 100.00
u_count_in_rst 100.00 100.00
u_count_in_timeout 100.00 100.00
u_count_nodata_in_count 100.00 100.00
u_count_nodata_in_endpoints 100.00 100.00
u_count_nodata_in_rst 100.00 100.00
u_count_out_count 100.00 100.00
u_count_out_datatog_out 100.00 100.00
u_count_out_drop_avout 100.00 100.00
u_count_out_drop_rx 100.00 100.00
u_count_out_endpoints 100.00 100.00
u_count_out_ign_avsetup 100.00 100.00
u_count_out_rst 100.00 100.00
u_ep_in_enable_enable_0 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_1 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_10 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_11 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_2 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_3 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_4 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_5 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_6 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_7 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_8 100.00 100.00 100.00 100.00
u_ep_in_enable_enable_9 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_0 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_1 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_10 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_11 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_2 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_3 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_4 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_5 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_6 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_7 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_8 100.00 100.00 100.00 100.00
u_ep_out_enable_enable_9 100.00 100.00 100.00 100.00
u_fifo_ctrl0_qe 100.00 100.00 100.00
u_fifo_ctrl_avout_rst 100.00 100.00 100.00 100.00
u_fifo_ctrl_avsetup_rst 100.00 100.00 100.00 100.00
u_fifo_ctrl_rx_rst 100.00 100.00 100.00 100.00
u_in_data_toggle_mask 60.00 60.00
u_in_data_toggle_status 100.00 100.00
u_in_iso_iso_0 100.00 100.00 100.00 100.00
u_in_iso_iso_1 100.00 100.00 100.00 100.00
u_in_iso_iso_10 100.00 100.00 100.00 100.00
u_in_iso_iso_11 100.00 100.00 100.00 100.00
u_in_iso_iso_2 100.00 100.00 100.00 100.00
u_in_iso_iso_3 100.00 100.00 100.00 100.00
u_in_iso_iso_4 100.00 100.00 100.00 100.00
u_in_iso_iso_5 100.00 100.00 100.00 100.00
u_in_iso_iso_6 100.00 100.00 100.00 100.00
u_in_iso_iso_7 100.00 100.00 100.00 100.00
u_in_iso_iso_8 100.00 100.00 100.00 100.00
u_in_iso_iso_9 100.00 100.00 100.00 100.00
u_in_sent_sent_0 100.00 100.00 100.00 100.00
u_in_sent_sent_1 100.00 100.00 100.00 100.00
u_in_sent_sent_10 100.00 100.00 100.00 100.00
u_in_sent_sent_11 100.00 100.00 100.00 100.00
u_in_sent_sent_2 100.00 100.00 100.00 100.00
u_in_sent_sent_3 100.00 100.00 100.00 100.00
u_in_sent_sent_4 100.00 100.00 100.00 100.00
u_in_sent_sent_5 100.00 100.00 100.00 100.00
u_in_sent_sent_6 100.00 100.00 100.00 100.00
u_in_sent_sent_7 100.00 100.00 100.00 100.00
u_in_sent_sent_8 100.00 100.00 100.00 100.00
u_in_sent_sent_9 100.00 100.00 100.00 100.00
u_in_stall_endpoint_0 100.00 100.00 100.00 100.00
u_in_stall_endpoint_1 100.00 100.00 100.00 100.00
u_in_stall_endpoint_10 100.00 100.00 100.00 100.00
u_in_stall_endpoint_11 100.00 100.00 100.00 100.00
u_in_stall_endpoint_2 100.00 100.00 100.00 100.00
u_in_stall_endpoint_3 100.00 100.00 100.00 100.00
u_in_stall_endpoint_4 100.00 100.00 100.00 100.00
u_in_stall_endpoint_5 100.00 100.00 100.00 100.00
u_in_stall_endpoint_6 100.00 100.00 100.00 100.00
u_in_stall_endpoint_7 100.00 100.00 100.00 100.00
u_in_stall_endpoint_8 100.00 100.00 100.00 100.00
u_in_stall_endpoint_9 100.00 100.00 100.00 100.00
u_intr_enable_av_out_empty 100.00 100.00 100.00 100.00
u_intr_enable_av_overflow 100.00 100.00 100.00 100.00
u_intr_enable_av_setup_empty 100.00 100.00 100.00 100.00
u_intr_enable_disconnected 100.00 100.00 100.00 100.00
u_intr_enable_frame 100.00 100.00 100.00 100.00
u_intr_enable_host_lost 100.00 100.00 100.00 100.00
u_intr_enable_link_in_err 100.00 100.00 100.00 100.00
u_intr_enable_link_out_err 100.00 100.00 100.00 100.00
u_intr_enable_link_reset 100.00 100.00 100.00 100.00
u_intr_enable_link_resume 100.00 100.00 100.00 100.00
u_intr_enable_link_suspend 100.00 100.00 100.00 100.00
u_intr_enable_pkt_received 100.00 100.00 100.00 100.00
u_intr_enable_pkt_sent 100.00 100.00 100.00 100.00
u_intr_enable_powered 100.00 100.00 100.00 100.00
u_intr_enable_rx_bitstuff_err 100.00 100.00 100.00 100.00
u_intr_enable_rx_crc_err 100.00 100.00 100.00 100.00
u_intr_enable_rx_full 100.00 100.00 100.00 100.00
u_intr_enable_rx_pid_err 100.00 100.00 100.00 100.00
u_intr_state_av_out_empty 62.59 77.78 50.00 60.00
u_intr_state_av_overflow 100.00 100.00 100.00 100.00
u_intr_state_av_setup_empty 62.59 77.78 50.00 60.00
u_intr_state_disconnected 100.00 100.00 100.00 100.00
u_intr_state_frame 100.00 100.00 100.00 100.00
u_intr_state_host_lost 100.00 100.00 100.00 100.00
u_intr_state_link_in_err 100.00 100.00 100.00 100.00
u_intr_state_link_out_err 100.00 100.00 100.00 100.00
u_intr_state_link_reset 100.00 100.00 100.00 100.00
u_intr_state_link_resume 100.00 100.00 100.00 100.00
u_intr_state_link_suspend 100.00 100.00 100.00 100.00
u_intr_state_pkt_received 62.59 77.78 50.00 60.00
u_intr_state_pkt_sent 62.59 77.78 50.00 60.00
u_intr_state_powered 100.00 100.00 100.00 100.00
u_intr_state_rx_bitstuff_err 100.00 100.00 100.00 100.00
u_intr_state_rx_crc_err 100.00 100.00 100.00 100.00
u_intr_state_rx_full 62.59 77.78 50.00 60.00
u_intr_state_rx_pid_err 100.00 100.00 100.00 100.00
u_intr_test_av_out_empty 100.00 100.00
u_intr_test_av_overflow 100.00 100.00
u_intr_test_av_setup_empty 100.00 100.00
u_intr_test_disconnected 100.00 100.00
u_intr_test_frame 100.00 100.00
u_intr_test_host_lost 100.00 100.00
u_intr_test_link_in_err 100.00 100.00
u_intr_test_link_out_err 100.00 100.00
u_intr_test_link_reset 100.00 100.00
u_intr_test_link_resume 100.00 100.00
u_intr_test_link_suspend 100.00 100.00
u_intr_test_pkt_received 100.00 100.00
u_intr_test_pkt_sent 100.00 100.00
u_intr_test_powered 100.00 100.00
u_intr_test_rx_bitstuff_err 100.00 100.00
u_intr_test_rx_crc_err 100.00 100.00
u_intr_test_rx_full 100.00 100.00
u_intr_test_rx_pid_err 100.00 100.00
u_out_data_toggle_mask 60.00 60.00
u_out_data_toggle_status 100.00 100.00
u_out_iso_iso_0 100.00 100.00 100.00 100.00
u_out_iso_iso_1 100.00 100.00 100.00 100.00
u_out_iso_iso_10 100.00 100.00 100.00 100.00
u_out_iso_iso_11 100.00 100.00 100.00 100.00
u_out_iso_iso_2 100.00 100.00 100.00 100.00
u_out_iso_iso_3 100.00 100.00 100.00 100.00
u_out_iso_iso_4 100.00 100.00 100.00 100.00
u_out_iso_iso_5 100.00 100.00 100.00 100.00
u_out_iso_iso_6 100.00 100.00 100.00 100.00
u_out_iso_iso_7 100.00 100.00 100.00 100.00
u_out_iso_iso_8 100.00 100.00 100.00 100.00
u_out_iso_iso_9 100.00 100.00 100.00 100.00
u_out_stall_endpoint_0 100.00 100.00 100.00 100.00
u_out_stall_endpoint_1 100.00 100.00 100.00 100.00
u_out_stall_endpoint_10 100.00 100.00 100.00 100.00
u_out_stall_endpoint_11 100.00 100.00 100.00 100.00
u_out_stall_endpoint_2 100.00 100.00 100.00 100.00
u_out_stall_endpoint_3 100.00 100.00 100.00 100.00
u_out_stall_endpoint_4 100.00 100.00 100.00 100.00
u_out_stall_endpoint_5 100.00 100.00 100.00 100.00
u_out_stall_endpoint_6 100.00 100.00 100.00 100.00
u_out_stall_endpoint_7 100.00 100.00 100.00 100.00
u_out_stall_endpoint_8 100.00 100.00 100.00 100.00
u_out_stall_endpoint_9 100.00 100.00 100.00 100.00
u_phy_config_eop_single_bit 100.00 100.00 100.00 100.00
u_phy_config_pinflip 100.00 100.00 100.00 100.00
u_phy_config_tx_osc_test_mode 100.00 100.00 100.00 100.00
u_phy_config_tx_use_d_se0 100.00 100.00 100.00 100.00
u_phy_config_usb_ref_disable 100.00 100.00 100.00 100.00
u_phy_config_use_diff_rcvr 100.00 100.00 100.00 100.00
u_phy_pins_drive_d_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_dn_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_dn_pullup_en_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_dp_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_dp_pullup_en_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_en 100.00 100.00 100.00 100.00
u_phy_pins_drive_oe_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_rx_enable_o 100.00 100.00 100.00 100.00
u_phy_pins_drive_se0_o 100.00 100.00 100.00 100.00
u_phy_pins_sense_pwr_sense 100.00 100.00
u_phy_pins_sense_rx_d_i 100.00 100.00
u_phy_pins_sense_rx_dn_i 100.00 100.00
u_phy_pins_sense_rx_dp_i 100.00 100.00
u_phy_pins_sense_tx_d_o 100.00 100.00
u_phy_pins_sense_tx_dn_o 100.00 100.00
u_phy_pins_sense_tx_dp_o 100.00 100.00
u_phy_pins_sense_tx_oe_o 100.00 100.00
u_phy_pins_sense_tx_se0_o 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.69 97.14 97.62 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_rxenable_out_out_0 100.00 100.00 100.00 100.00
u_rxenable_out_out_1 100.00 100.00 100.00 100.00
u_rxenable_out_out_10 100.00 100.00 100.00 100.00
u_rxenable_out_out_11 100.00 100.00 100.00 100.00
u_rxenable_out_out_2 100.00 100.00 100.00 100.00
u_rxenable_out_out_3 100.00 100.00 100.00 100.00
u_rxenable_out_out_4 100.00 100.00 100.00 100.00
u_rxenable_out_out_5 100.00 100.00 100.00 100.00
u_rxenable_out_out_6 100.00 100.00 100.00 100.00
u_rxenable_out_out_7 100.00 100.00 100.00 100.00
u_rxenable_out_out_8 100.00 100.00 100.00 100.00
u_rxenable_out_out_9 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_0 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_1 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_10 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_11 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_2 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_3 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_4 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_5 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_6 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_7 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_8 100.00 100.00 100.00 100.00
u_rxenable_setup_setup_9 100.00 100.00 100.00 100.00
u_rxfifo_buffer 100.00 100.00
u_rxfifo_ep 100.00 100.00
u_rxfifo_setup 100.00 100.00
u_rxfifo_size 100.00 100.00
u_set_nak_out_enable_0 100.00 100.00 100.00 100.00
u_set_nak_out_enable_1 100.00 100.00 100.00 100.00
u_set_nak_out_enable_10 100.00 100.00 100.00 100.00
u_set_nak_out_enable_11 100.00 100.00 100.00 100.00
u_set_nak_out_enable_2 100.00 100.00 100.00 100.00
u_set_nak_out_enable_3 100.00 100.00 100.00 100.00
u_set_nak_out_enable_4 100.00 100.00 100.00 100.00
u_set_nak_out_enable_5 100.00 100.00 100.00 100.00
u_set_nak_out_enable_6 100.00 100.00 100.00 100.00
u_set_nak_out_enable_7 100.00 100.00 100.00 100.00
u_set_nak_out_enable_8 100.00 100.00 100.00 100.00
u_set_nak_out_enable_9 100.00 100.00 100.00 100.00
u_socket 98.24 98.75 98.21 96.00 100.00
u_usbctrl0_qe 100.00 100.00 100.00
u_usbctrl_device_address 100.00 100.00 100.00 100.00
u_usbctrl_enable 100.00 100.00 100.00 100.00
u_usbctrl_resume_link_active 100.00 100.00 100.00 100.00
u_usbstat_av_out_depth 100.00 100.00
u_usbstat_av_out_full 100.00 100.00
u_usbstat_av_setup_depth 100.00 100.00
u_usbstat_av_setup_full 100.00 100.00
u_usbstat_frame 100.00 100.00
u_usbstat_host_lost 100.00 100.00
u_usbstat_link_state 100.00 100.00
u_usbstat_rx_depth 100.00 100.00
u_usbstat_rx_empty 100.00 100.00
u_usbstat_sense 100.00 100.00
u_wake_control_cdc 98.13 96.08 96.43 100.00 100.00
u_wake_control_suspend_req 100.00 100.00
u_wake_control_wake_ack 100.00 100.00
u_wake_events_bus_not_idle 62.59 77.78 50.00 60.00
u_wake_events_bus_reset 62.59 77.78 50.00 60.00
u_wake_events_cdc 71.94 90.62 52.94 84.21 60.00
u_wake_events_disconnected 62.59 77.78 50.00 60.00
u_wake_events_module_active 62.59 77.78 50.00 60.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usbdev_reg_top
Line No.TotalCoveredPercent
TOTAL81881699.76
ALWAYS7544100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN10211100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10611100.00
ALWAYS13233100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17011100.00
ALWAYS789100.00
CONT_ASSIGN81611100.00
ALWAYS8321010100.00
CONT_ASSIGN184911100.00
CONT_ASSIGN186411100.00
CONT_ASSIGN188011100.00
CONT_ASSIGN189611100.00
CONT_ASSIGN191211100.00
CONT_ASSIGN192811100.00
CONT_ASSIGN194411100.00
CONT_ASSIGN196011100.00
CONT_ASSIGN197611100.00
CONT_ASSIGN199211100.00
CONT_ASSIGN200811100.00
CONT_ASSIGN202411100.00
CONT_ASSIGN204011100.00
CONT_ASSIGN205611100.00
CONT_ASSIGN207211100.00
CONT_ASSIGN208811100.00
CONT_ASSIGN210411100.00
CONT_ASSIGN212011100.00
CONT_ASSIGN213611100.00
CONT_ASSIGN214211100.00
CONT_ASSIGN215611100.00
CONT_ASSIGN222411100.00
CONT_ASSIGN306311100.00
CONT_ASSIGN307711100.00
CONT_ASSIGN308311100.00
CONT_ASSIGN309711100.00
CONT_ASSIGN743711100.00
CONT_ASSIGN745211100.00
CONT_ASSIGN746811100.00
CONT_ASSIGN747411100.00
CONT_ASSIGN748911100.00
CONT_ASSIGN750511100.00
CONT_ASSIGN805711100.00
CONT_ASSIGN807211100.00
CONT_ASSIGN808811100.00
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WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
75 1 1
76 1 1
77 1 1
78 1 1
MISSING_ELSE
84 1 1
102 1 1
103 1 1
105 1 1
106 1 1
132 1 1
138 1 1
139 1 1
MISSING_ELSE
169 1 1
170 1 1
789 0 1
816 1 1
832 1 1
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8305 unreachable
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8424 unreachable
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9599 1 1
9600 1 1
9601 1 1
9602 1 1
9603 1 1
9604 1 1
9605 1 1
9606 1 1
9610 1 1
9611 1 1
9612 1 1
9613 1 1
9614 1 1
9615 1 1
9616 1 1
9617 1 1
9618 1 1
9619 1 1
9620 1 1
9621 1 1
9625 1 1
9626 1 1
9627 1 1
9628 1 1
9629 1 1
9630 1 1
9631 1 1
9632 1 1
9633 1 1
9634 1 1
9635 1 1
9636 1 1
9640 1 1
9641 1 1
9642 1 1
9643 1 1
9644 1 1
9645 1 1
9646 1 1
9647 1 1
9648 1 1
9649 1 1
9650 1 1
9651 1 1
9655 1 1
9656 1 1
9657 1 1
9658 1 1
9659 1 1
9663 1 1
9664 1 1
9665 1 1
9666 1 1
9667 1 1
9671 1 1
9672 1 1
9673 1 1
9674 1 1
9675 1 1
9679 1 1
9680 1 1
9681 1 1
9682 1 1
9683 1 1
9687 1 1
9688 1 1
9689 1 1
9690 1 1
9691 1 1
9695 1 1
9696 1 1
9697 1 1
9698 1 1
9699 1 1
9703 1 1
9704 1 1
9705 1 1
9706 1 1
9707 1 1
9711 1 1
9712 1 1
9713 1 1
9714 1 1
9715 1 1
9719 1 1
9720 1 1
9721 1 1
9722 1 1
9723 1 1
9727 1 1
9728 1 1
9729 1 1
9730 1 1
9731 1 1
9735 1 1
9736 1 1
9737 1 1
9738 1 1
9739 1 1
9743 1 1
9744 1 1
9745 1 1
9746 1 1
9747 1 1
9751 1 1
9752 1 1
9753 1 1
9754 1 1
9755 1 1
9756 1 1
9757 1 1
9758 1 1
9759 1 1
9760 1 1
9761 1 1
9762 1 1
9766 1 1
9767 1 1
9768 1 1
9769 1 1
9770 1 1
9771 1 1
9772 1 1
9773 1 1
9774 1 1
9775 1 1
9776 1 1
9777 1 1
9781 1 1
9782 1 1
9786 1 1
9787 1 1
9791 1 1
9792 1 1
9793 1 1
9794 1 1
9795 1 1
9796 1 1
9797 1 1
9798 1 1
9799 1 1
9803 1 1
9804 1 1
9805 1 1
9806 1 1
9807 1 1
9808 1 1
9809 1 1
9810 1 1
9811 1 1
9815 1 1
9816 1 1
9817 1 1
9818 1 1
9819 1 1
9820 1 1
9824 1 1
9827 1 1
9830 1 1
9831 1 1
9832 1 1
9836 1 1
9837 1 1
9838 1 1
9839 1 1
9840 1 1
9841 1 1
9842 1 1
9846 1 1
9847 1 1
9848 1 1
9849 1 1
9850 1 1
9851 1 1
9855 1 1
9856 1 1
9857 1 1
9861 1 1
9862 1 1
9863 1 1
9864 1 1
9865 1 1
9866 1 1
9881 1 1
9883 1 1
9884 1 1
9886 1 1
9889 1 1
9904 1 1
9905 1 1


Cond Coverage for Module : usbdev_reg_top
TotalCoveredPercent
Conditions47746998.32
Logical47746998.32
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
65-928899.05
9293-988192.59

Branch Coverage for Module : usbdev_reg_top
Line No.TotalCoveredPercent
Branches 56 56 100.00
TERNARY 8729 2 2 100.00
IF 75 3 3 100.00
TERNARY 132 2 2 100.00
IF 138 2 2 100.00
CASE 9432 44 44 100.00
CASE 9884 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 8729 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 75 if ((!rst_ni)) -2-: 77 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T191,T192,T193
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 132 ((tl_i.a_address[(AW - 1):0] inside {[2048:4095]})) ?

Branches:
-1-StatusTests
1 Covered T1,T31,T29
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 if (intg_err)

Branches:
-1-StatusTests
1 Covered T198,T220,T225
0 Covered T1,T2,T3


LineNo. Expression -1-: 9432 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
addr_hit[29] Covered T1,T2,T3
addr_hit[30] Covered T1,T2,T3
addr_hit[31] Covered T1,T2,T3
addr_hit[32] Covered T1,T2,T3
addr_hit[33] Covered T1,T2,T3
addr_hit[34] Covered T1,T2,T3
addr_hit[35] Covered T1,T2,T3
addr_hit[36] Covered T1,T2,T3
addr_hit[37] Covered T1,T2,T3
addr_hit[38] Covered T1,T2,T3
addr_hit[39] Covered T1,T2,T3
addr_hit[40] Covered T1,T2,T3
addr_hit[41] Covered T1,T2,T3
addr_hit[42] Covered T1,T2,T3
default Covered T1,T2,T3


LineNo. Expression -1-: 9884 case (1'b1)

Branches:
-1-StatusTests
addr_hit[36] Covered T1,T2,T3
addr_hit[37] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : usbdev_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 506885191 29341255 0 0
reAfterRv 506885191 29341255 0 0
rePulse 506885191 28994968 0 0
wePulse 506885191 346287 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 506885191 29341255 0 0
T1 24978 78 0 0
T2 8806 11 0 0
T3 8916 10 0 0
T25 10525 14 0 0
T26 9273 10 0 0
T27 9967 14 0 0
T28 9970 10 0 0
T30 2374 5 0 0
T31 8444 983 0 0
T32 7089 10 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 506885191 29341255 0 0
T1 24978 78 0 0
T2 8806 11 0 0
T3 8916 10 0 0
T25 10525 14 0 0
T26 9273 10 0 0
T27 9967 14 0 0
T28 9970 10 0 0
T30 2374 5 0 0
T31 8444 983 0 0
T32 7089 10 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 506885191 28994968 0 0
T1 24978 61 0 0
T2 8806 2 0 0
T3 8916 2 0 0
T25 10525 4 0 0
T26 9273 2 0 0
T27 9967 4 0 0
T28 9970 2 0 0
T30 2374 2 0 0
T31 8444 186 0 0
T32 7089 2 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 506885191 346287 0 0
T1 24978 17 0 0
T2 8806 9 0 0
T3 8916 8 0 0
T25 10525 10 0 0
T26 9273 8 0 0
T27 9967 10 0 0
T28 9970 8 0 0
T30 2374 3 0 0
T31 8444 797 0 0
T32 7089 8 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%