Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15611852	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16368658	1		T1	890		T2	18		T3	7433

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31368452	1		T1	2120		T2	19		T3	4161
values[0x0]	305023	1		T1	338		T2	2		T3	1810
values[0x1]	307035	1		T1	311		T2	5		T3	1845

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12445626	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19534884	1		T1	1544		T2	20		T3	7497

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	210668	1		T1	9		T3	26		T4	20
valid_sources[0x01]	177212	1		T1	9		T3	35		T4	36
valid_sources[0x02]	217829	1		T1	15		T3	30		T4	46
valid_sources[0x03]	148917	1		T1	11		T3	28		T4	31
valid_sources[0x04]	330728	1		T1	7		T3	34		T4	27
valid_sources[0x05]	95518	1		T1	9		T3	37		T4	23
valid_sources[0x06]	95565	1		T1	11		T3	35		T4	41
valid_sources[0x07]	217949	1		T1	11		T3	35		T4	42
valid_sources[0x08]	94379	1		T1	10		T3	35		T4	14
valid_sources[0x09]	94625	1		T1	7		T3	21		T4	33
valid_sources[0x0a]	95736	1		T1	15		T3	34		T4	34
valid_sources[0x0b]	94884	1		T1	16		T3	31		T4	26
valid_sources[0x0c]	94851	1		T1	7		T3	19		T4	30
valid_sources[0x0d]	94463	1		T1	8		T3	23		T4	33
valid_sources[0x0e]	138862	1		T1	7		T3	29		T4	21
valid_sources[0x0f]	247706	1		T1	10		T3	35		T4	25
valid_sources[0x10]	197277	1		T1	8		T3	32		T4	32
valid_sources[0x11]	94636	1		T1	12		T3	38		T4	24
valid_sources[0x12]	93777	1		T1	11		T3	26		T4	28
valid_sources[0x13]	94504	1		T1	11		T3	34		T4	42
valid_sources[0x14]	95232	1		T1	11		T3	33		T4	34
valid_sources[0x15]	93665	1		T1	20		T3	35		T4	22
valid_sources[0x16]	93695	1		T1	13		T2	2		T3	16
valid_sources[0x17]	94856	1		T1	9		T3	29		T4	27
valid_sources[0x18]	94695	1		T1	13		T3	15		T4	14
valid_sources[0x19]	97175	1		T1	5		T3	40		T4	27
valid_sources[0x1a]	240445	1		T1	7		T3	28		T4	28
valid_sources[0x1b]	203308	1		T1	17		T3	38		T4	15
valid_sources[0x1c]	96656	1		T1	11		T3	35		T4	39
valid_sources[0x1d]	94832	1		T1	12		T3	31		T4	28
valid_sources[0x1e]	149641	1		T1	10		T3	38		T4	34
valid_sources[0x1f]	258550	1		T1	3		T3	34		T4	29
valid_sources[0x20]	95908	1		T1	11		T3	30		T4	24
valid_sources[0x21]	95846	1		T1	11		T3	34		T4	24
valid_sources[0x22]	93205	1		T1	9		T3	26		T4	19
valid_sources[0x23]	95037	1		T1	9		T3	35		T4	21
valid_sources[0x24]	95906	1		T1	12		T3	25		T4	20
valid_sources[0x25]	93845	1		T1	13		T3	18		T4	38
valid_sources[0x26]	121705	1		T1	16		T3	22		T4	31
valid_sources[0x27]	94557	1		T1	12		T2	2		T3	38
valid_sources[0x28]	94887	1		T1	9		T3	41		T4	21
valid_sources[0x29]	98569	1		T1	9		T3	23		T4	29
valid_sources[0x2a]	96179	1		T1	11		T3	32		T4	32
valid_sources[0x2b]	197513	1		T1	12		T3	37		T4	45
valid_sources[0x2c]	94640	1		T1	9		T3	21		T4	38
valid_sources[0x2d]	117805	1		T1	8		T3	31		T4	19
valid_sources[0x2e]	98129	1		T1	12		T3	46		T4	42
valid_sources[0x2f]	109555	1		T1	14		T3	27		T4	36
valid_sources[0x30]	98047	1		T1	11		T3	38		T4	24
valid_sources[0x31]	97088	1		T1	10		T3	21		T4	29
valid_sources[0x32]	205802	1		T1	11		T3	35		T4	18
valid_sources[0x33]	95549	1		T1	12		T3	25		T4	28
valid_sources[0x34]	96622	1		T1	10		T3	28		T4	17
valid_sources[0x35]	98337	1		T1	7		T3	37		T4	32
valid_sources[0x36]	95970	1		T1	8		T3	35		T4	33
valid_sources[0x37]	123025	1		T1	9		T3	17		T4	17
valid_sources[0x38]	95292	1		T1	15		T3	30		T4	34
valid_sources[0x39]	100767	1		T1	16		T3	22		T4	21
valid_sources[0x3a]	96231	1		T1	9		T2	1		T3	30
valid_sources[0x3b]	183992	1		T1	9		T3	28		T4	27
valid_sources[0x3c]	96654	1		T1	8		T3	26		T4	24
valid_sources[0x3d]	95059	1		T1	8		T3	27		T4	41
valid_sources[0x3e]	95146	1		T1	13		T3	31		T4	50
valid_sources[0x3f]	94228	1		T1	9		T3	33		T4	39
valid_sources[0x40]	193706	1		T1	10		T3	21		T4	18
valid_sources[0x41]	96347	1		T1	11		T3	26		T4	34
valid_sources[0x42]	95106	1		T1	8		T3	28		T4	25
valid_sources[0x43]	145619	1		T1	14		T3	30		T4	23
valid_sources[0x44]	94994	1		T1	13		T3	32		T4	33
valid_sources[0x45]	96909	1		T1	7		T3	27		T4	19
valid_sources[0x46]	136319	1		T1	14		T3	31		T4	50
valid_sources[0x47]	94684	1		T1	14		T3	26		T4	29
valid_sources[0x48]	196156	1		T1	9		T3	33		T4	27
valid_sources[0x49]	122778	1		T1	12		T3	33		T4	26
valid_sources[0x4a]	95277	1		T1	9		T3	17		T4	28
valid_sources[0x4b]	95103	1		T1	13		T3	37		T4	39
valid_sources[0x4c]	94193	1		T1	9		T3	31		T4	35
valid_sources[0x4d]	109778	1		T1	16		T3	34		T4	46
valid_sources[0x4e]	242530	1		T1	11		T3	24		T4	41
valid_sources[0x4f]	130218	1		T1	14		T3	35		T4	24
valid_sources[0x50]	100128	1		T1	6		T3	24		T4	40
valid_sources[0x51]	96858	1		T1	13		T3	19		T4	40
valid_sources[0x52]	95503	1		T1	12		T3	26		T4	18
valid_sources[0x53]	95941	1		T1	14		T3	44		T4	38
valid_sources[0x54]	94858	1		T1	15		T3	22		T4	33
valid_sources[0x55]	269364	1		T1	13		T3	37		T4	38
valid_sources[0x56]	95932	1		T1	12		T3	32		T4	37
valid_sources[0x57]	94642	1		T1	9		T3	26		T4	14
valid_sources[0x58]	95667	1		T1	15		T3	30		T4	18
valid_sources[0x59]	119038	1		T1	11		T3	27		T4	31
valid_sources[0x5a]	210357	1		T1	12		T3	25		T4	28
valid_sources[0x5b]	95663	1		T1	9		T3	32		T4	30
valid_sources[0x5c]	141068	1		T1	7		T3	32		T4	50
valid_sources[0x5d]	94914	1		T1	4		T3	35		T4	32
valid_sources[0x5e]	95105	1		T1	11		T3	54		T4	43
valid_sources[0x5f]	97076	1		T1	9		T3	26		T4	25
valid_sources[0x60]	132095	1		T1	12		T3	34		T4	35
valid_sources[0x61]	96314	1		T1	18		T3	24		T4	22
valid_sources[0x62]	95079	1		T1	9		T3	24		T4	46
valid_sources[0x63]	222157	1		T1	9		T3	32		T4	47
valid_sources[0x64]	94814	1		T1	14		T3	27		T4	30
valid_sources[0x65]	146323	1		T1	10		T3	35		T4	24
valid_sources[0x66]	95367	1		T1	12		T3	31		T4	31
valid_sources[0x67]	95600	1		T1	11		T3	39		T4	38
valid_sources[0x68]	95844	1		T1	18		T3	28		T4	45
valid_sources[0x69]	139957	1		T1	9		T3	34		T4	31
valid_sources[0x6a]	94659	1		T1	10		T3	41		T4	21
valid_sources[0x6b]	95044	1		T1	5		T3	18		T4	38
valid_sources[0x6c]	106060	1		T1	15		T3	26		T4	36
valid_sources[0x6d]	123197	1		T1	7		T3	35		T4	20
valid_sources[0x6e]	95930	1		T1	5		T3	34		T4	26
valid_sources[0x6f]	93822	1		T1	13		T3	32		T4	34
valid_sources[0x70]	95822	1		T1	18		T3	40		T4	34
valid_sources[0x71]	95466	1		T1	6		T3	33		T4	26
valid_sources[0x72]	94579	1		T1	5		T3	38		T4	26
valid_sources[0x73]	95351	1		T1	11		T3	21		T4	49
valid_sources[0x74]	139286	1		T1	12		T3	34		T4	39
valid_sources[0x75]	133483	1		T1	13		T3	24		T4	40
valid_sources[0x76]	94264	1		T1	13		T3	27		T4	19
valid_sources[0x77]	94721	1		T1	13		T3	28		T4	29
valid_sources[0x78]	137872	1		T1	11		T3	30		T4	38
valid_sources[0x79]	313619	1		T1	15		T3	22		T4	27
valid_sources[0x7a]	98178	1		T1	7		T3	43		T4	38
valid_sources[0x7b]	123148	1		T1	11		T3	29		T4	20
valid_sources[0x7c]	95183	1		T1	13		T3	26		T4	35
valid_sources[0x7d]	95887	1		T1	11		T3	36		T4	37
valid_sources[0x7e]	95682	1		T1	9		T3	29		T4	23
valid_sources[0x7f]	95724	1		T1	6		T3	36		T4	23
valid_sources[0x80]	95376	1		T1	8		T3	28		T4	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15880637

1

T1

299

T2

16

T3

4005

values[0x0]

all_enables

biggest_size

251145

1

T1

318

T2

1

T3

1707

values[0x1]

all_enables

biggest_size

236876

1

T1

273

T2

1

T3

1721