Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	15625153	1		T1	1879		T2	8		T3	383
full_word	16369585	1		T1	890		T2	18		T3	7433

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31994438	1		T1	2769		T2	26		T3	7816
auto[TlIntgErrCmd]	106	1		T209	4		T233	6		T234	4
auto[TlIntgErrData]	102	1		T209	9		T233	7		T234	1
auto[TlIntgErrBoth]	92	1		T209	7		T233	7		T234	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31370204	1		T1	2120		T2	19		T3	4161
auto[1]	624534	1		T1	649		T2	7		T3	3655

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15489261	1		T1	1821		T2	3		T3	156
auto[TlIntgErrNone]	partial	auto[1]	135619	1		T1	58		T2	5		T3	227
auto[TlIntgErrNone]	full_word	auto[0]	15880806	1		T1	299		T2	16		T3	4005
auto[TlIntgErrNone]	full_word	auto[1]	488752	1		T1	591		T2	2		T3	3428
auto[TlIntgErrCmd]	partial	auto[0]	46	1		T209	2		T233	5		T234	3
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T209	2		T233	1		T310	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T310	1		T311	1		T313	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T234	1		T310	1		T312	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T209	2		T233	4		T310	3
auto[TlIntgErrData]	partial	auto[1]	54	1		T209	6		T233	3		T310	3
auto[TlIntgErrData]	full_word	auto[0]	6	1		T209	1		T234	1		T312	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T310	1		T314	1		T315	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T209	4		T233	3		T234	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T209	2		T233	4		T234	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T209	1		T289	1		T316	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T317	1		-	-		-	-