Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	503662787	10933	0	0
ep_in_enable_rd_A	503662787	3620	0	0
ep_out_enable_rd_A	503662787	3435	0	0
in_iso_rd_A	503662787	3284	0	0
intr_enable_rd_A	503662787	4581	0	0
out_iso_rd_A	503662787	3227	0	0
phy_config_rd_A	503662787	2205	0	0
phy_pins_drive_rd_A	503662787	2739	0	0
rxenable_setup_rd_A	503662787	3352	0	0
set_nak_out_rd_A	503662787	3269	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503662787	10933	0	0
T207	4985	17	0	0
T208	6934	12	0	0
T209	46646	3	0	0
T210	5253	7	0	0
T232	6396	9	0	0
T233	23434	3	0	0
T234	51834	2	0	0
T240	4095	373	0	0
T241	5675	756	0	0
T243	6918	234	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503662787	3620	0	0
T208	6934	2	0	0
T232	6396	10	0	0
T234	51834	195	0	0
T268	2878	33	0	0
T271	3526	38	0	0
T281	10079	69	0	0
T282	14114	85	0	0
T288	2080	5	0	0
T289	23652	160	0	0
T290	26680	365	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503662787	3435	0	0
T208	6934	1	0	0
T232	6396	56	0	0
T234	51834	370	0	0
T268	2878	43	0	0
T271	3526	27	0	0
T281	10079	32	0	0
T282	14114	48	0	0
T288	2080	65	0	0
T289	23652	244	0	0
T290	26680	341	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503662787	3284	0	0
T208	6934	54	0	0
T232	6396	41	0	0
T234	51834	186	0	0
T268	2878	21	0	0
T271	3526	4	0	0
T281	10079	60	0	0
T282	14114	55	0	0
T288	2080	7	0	0
T289	23652	234	0	0
T290	26680	384	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503662787	4581	0	0
T208	6934	5	0	0
T232	6396	107	0	0
T234	51834	341	0	0
T268	2878	50	0	0
T281	10079	78	0	0
T282	14114	63	0	0
T288	2080	3	0	0
T291	3362	10	0	0
T292	2708	6	0	0
T293	2800	8	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503662787	3227	0	0
T208	6934	63	0	0
T232	6396	9	0	0
T234	51834	202	0	0
T268	2878	5	0	0
T271	3526	42	0	0
T281	10079	52	0	0
T282	14114	38	0	0
T288	2080	47	0	0
T289	23652	156	0	0
T290	26680	260	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503662787	2205	0	0
T208	6934	19	0	0
T232	6396	27	0	0
T234	51834	153	0	0
T268	2878	1	0	0
T271	3526	14	0	0
T281	10079	29	0	0
T282	14114	14	0	0
T288	2080	1	0	0
T289	23652	174	0	0
T290	26680	130	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503662787	2739	0	0
T208	6934	36	0	0
T232	6396	22	0	0
T234	51834	200	0	0
T268	2878	13	0	0
T271	3526	24	0	0
T281	10079	80	0	0
T282	14114	11	0	0
T288	2080	1	0	0
T289	23652	179	0	0
T290	26680	134	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503662787	3352	0	0
T208	6934	14	0	0
T232	6396	5	0	0
T234	51834	271	0	0
T268	2878	11	0	0
T271	3526	52	0	0
T281	10079	26	0	0
T282	14114	72	0	0
T288	2080	3	0	0
T289	23652	151	0	0
T290	26680	180	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503662787	3269	0	0
T208	6934	66	0	0
T232	6396	27	0	0
T234	51834	291	0	0
T268	2878	18	0	0
T271	3526	4	0	0
T281	10079	27	0	0
T282	14114	33	0	0
T288	2080	36	0	0
T289	23652	272	0	0
T290	26680	311	0	0