Module Definition
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Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.52 100.00 55.56 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.52 100.00 55.56 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_se0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.22 100.00 66.67 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.22 100.00 66.67 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.93 100.00 77.78 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.93 100.00 77.78 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_oe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.63 100.00 88.89 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.63 100.00 88.89 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_dn


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_dp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT26,T27,T28

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT26,T27,T28
11CoveredT26,T27,T28

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 13086511 13074828 0 0
selKnown1 97 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 13086511 13074828 0 0
T1 5685 5680 0 0
T2 22 17 0 0
T3 30113 30108 0 0
T4 43886 43881 0 0
T5 18002 17997 0 0
T6 19976 19971 0 0
T29 336 331 0 0
T30 81 76 0 0
T31 298 293 0 0
T32 8 17 0 0
T33 0 2 0 0
T34 0 2 0 0
T35 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 97 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT26,T27,T28
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 144423 142314 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 144423 142314 0 0
T1 176 175 0 0
T2 1 0 0 0
T3 611 610 0 0
T4 65 64 0 0
T5 196 195 0 0
T6 175 174 0 0
T29 2 1 0 0
T30 2 1 0 0
T31 10 9 0 0
T32 1 0 0 0
T33 0 1 0 0
T34 0 1 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9666.67
Logical9666.67
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT26,T27,T28
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4273090 4270413 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4273090 4270413 0 0
T1 1779 1778 0 0
T2 7 6 0 0
T3 9649 9648 0 0
T4 14588 14587 0 0
T5 5884 5883 0 0
T6 6557 6556 0 0
T29 111 110 0 0
T30 26 25 0 0
T31 93 92 0 0
T32 0 6 0 0
T35 1 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT26,T27,T28

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT26,T27,T28
10Not Covered
11CoveredT26,T27,T28

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 144424 142314 0 0
selKnown1 50 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 144424 142314 0 0
T1 176 175 0 0
T2 1 0 0 0
T3 611 610 0 0
T4 65 64 0 0
T5 196 195 0 0
T6 175 174 0 0
T29 2 1 0 0
T30 2 1 0 0
T31 10 9 0 0
T32 1 0 0 0
T33 0 1 0 0
T34 0 1 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 50 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT27,T36,T37

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT27,T36,T37
10CoveredT26,T28,T38
11CoveredT27,T36,T37

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4251484 4249374 0 0
selKnown1 25 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4251484 4249374 0 0
T1 1775 1774 0 0
T2 6 5 0 0
T3 9593 9592 0 0
T4 14580 14579 0 0
T5 5842 5841 0 0
T6 6512 6511 0 0
T29 110 109 0 0
T30 25 24 0 0
T31 92 91 0 0
T32 6 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 25 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT28,T38,T37

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT28,T38,T37
10CoveredT26,T27,T39
11CoveredT28,T38,T37

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4273090 4270413 0 0
selKnown1 22 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4273090 4270413 0 0
T1 1779 1778 0 0
T2 7 6 0 0
T3 9649 9648 0 0
T4 14588 14587 0 0
T5 5884 5883 0 0
T6 6557 6556 0 0
T29 111 110 0 0
T30 26 25 0 0
T31 93 92 0 0
T32 0 6 0 0
T35 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 22 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%