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Module Instance : tb.dut.usbdev_avsetupfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.06 100.00 88.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.03 97.53 88.06 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.usbdev_avoutfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 100.00 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.06 100.00 88.24 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.03 97.53 88.06 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.usbdev_rxfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.53 100.00 86.11 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.03 97.53 88.06 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.33 95.00 75.00 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.43 98.59 78.81 92.31 100.00 gen_no_stubbed_memory.u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.62 100.00 62.50 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.64 95.00 72.22 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.43 98.59 78.81 92.31 100.00 gen_no_stubbed_memory.u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.32 95.00 77.27 85.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.43 98.59 78.81 92.31 100.00 gen_no_stubbed_memory.u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73

Go back
Module Instances:
tb.dut.usbdev_avsetupfifo
tb.dut.usbdev_avoutfifo
tb.dut.usbdev_rxfifo
tb.dut.u_reg.u_socket.fifo_h.reqfifo
tb.dut.u_reg.u_socket.fifo_h.rspfifo
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
Line Coverage for Instance : tb.dut.usbdev_avsetupfifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T85
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT69,T91
110Not Covered
111CoveredT1,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T5,T6
110Not Covered
111CoveredT1,T5,T6

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T5,T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 501774998 144843243 0 0
DepthKnown_A 501774998 501569118 0 0
RvalidKnown_A 501774998 501569118 0 0
WreadyKnown_A 501774998 501569118 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 501774998 144843243 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 144843243 0 0
T1 490926 431750 0 0
T2 9603 0 0 0
T3 688610 0 0 0
T4 244181 0 0 0
T5 384882 378581 0 0
T6 237679 231982 0 0
T29 16981 0 0 0
T30 7662 0 0 0
T31 17144 0 0 0
T35 7736 0 0 0
T51 0 579 0 0
T75 0 527452 0 0
T85 0 4669 0 0
T88 0 194203 0 0
T89 0 315205 0 0
T90 0 12025 0 0
T92 0 180465 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 144843243 0 0
T1 490926 431750 0 0
T2 9603 0 0 0
T3 688610 0 0 0
T4 244181 0 0 0
T5 384882 378581 0 0
T6 237679 231982 0 0
T29 16981 0 0 0
T30 7662 0 0 0
T31 17144 0 0 0
T35 7736 0 0 0
T51 0 579 0 0
T75 0 527452 0 0
T85 0 4669 0 0
T88 0 194203 0 0
T89 0 315205 0 0
T90 0 12025 0 0
T92 0 180465 0 0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1


Cond Coverage for Instance : tb.dut.usbdev_avoutfifo
TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT5,T6,T85
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT67,T68,T93
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo
Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.usbdev_avoutfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 501774998 285872200 0 0
DepthKnown_A 501774998 501569118 0 0
RvalidKnown_A 501774998 501569118 0 0
WreadyKnown_A 501774998 501569118 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 501774998 285872200 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 285872200 0 0
T1 490926 453340 0 0
T2 9603 1997 0 0
T3 688610 429507 0 0
T4 244181 0 0 0
T5 384882 378525 0 0
T6 237679 231966 0 0
T29 16981 1865 0 0
T30 7662 410 0 0
T31 17144 6052 0 0
T32 0 1659 0 0
T33 0 790 0 0
T35 7736 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 285872200 0 0
T1 490926 453340 0 0
T2 9603 1997 0 0
T3 688610 429507 0 0
T4 244181 0 0 0
T5 384882 378525 0 0
T6 237679 231966 0 0
T29 16981 1865 0 0
T30 7662 410 0 0
T31 17144 6052 0 0
T32 0 1659 0 0
T33 0 790 0 0
T35 7736 0 0 0

Line Coverage for Instance : tb.dut.usbdev_rxfifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.usbdev_rxfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT57,T58,T59
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.usbdev_rxfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.usbdev_rxfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 501774998 23840728 0 0
DepthKnown_A 501774998 501569118 0 0
RvalidKnown_A 501774998 501569118 0 0
WreadyKnown_A 501774998 501569118 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 501774998 23840728 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 23840728 0 0
T1 490926 240739 0 0
T2 9603 115 0 0
T3 688610 29536 0 0
T4 244181 0 0 0
T5 384882 2306 0 0
T6 237679 616 0 0
T29 16981 95 0 0
T30 7662 1452 0 0
T31 17144 567 0 0
T33 0 113 0 0
T34 0 91 0 0
T35 7736 0 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 23840728 0 0
T1 490926 240739 0 0
T2 9603 115 0 0
T3 688610 29536 0 0
T4 244181 0 0 0
T5 384882 2306 0 0
T6 237679 616 0 0
T29 16981 95 0 0
T30 7662 1452 0 0
T31 17144 567 0 0
T33 0 113 0 0
T34 0 91 0 0
T35 7736 0 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 503662787 32312077 0 0
DepthKnown_A 503662787 503402351 0 0
RvalidKnown_A 503662787 503402351 0 0
WreadyKnown_A 503662787 503402351 0 0
gen_passthru_fifo.paramCheckPass 2852 2852 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 32312077 0 0
T1 490926 2769 0 0
T2 9603 26 0 0
T3 688610 9770 0 0
T4 244181 7771 0 0
T5 384882 53587 0 0
T6 237679 115606 0 0
T29 16981 46 0 0
T30 7662 13 0 0
T31 17144 95 0 0
T35 7736 11 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2852 2852 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T35 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 503662787 42230693 0 0
DepthKnown_A 503662787 503402351 0 0
RvalidKnown_A 503662787 503402351 0 0
WreadyKnown_A 503662787 503402351 0 0
gen_passthru_fifo.paramCheckPass 2852 2852 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 42230693 0 0
T1 490926 2769 0 0
T2 9603 105 0 0
T3 688610 35820 0 0
T4 244181 24080 0 0
T5 384882 53587 0 0
T6 237679 115606 0 0
T29 16981 46 0 0
T30 7662 56 0 0
T31 17144 316 0 0
T35 7736 11 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2852 2852 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T35 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 503662787 857724 0 0
DepthKnown_A 503662787 503402351 0 0
RvalidKnown_A 503662787 503402351 0 0
WreadyKnown_A 503662787 503402351 0 0
gen_passthru_fifo.paramCheckPass 2852 2852 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 857724 0 0
T1 490926 526 0 0
T2 9603 14 0 0
T3 688610 6586 0 0
T4 244181 1504 0 0
T5 384882 0 0 0
T6 237679 0 0 0
T29 16981 12 0 0
T30 7662 0 0 0
T31 17144 35 0 0
T34 0 9 0 0
T35 7736 0 0 0
T51 0 17 0 0
T86 0 16 0 0
T87 0 16 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2852 2852 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T35 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 503662787 1604322 0 0
DepthKnown_A 503662787 503402351 0 0
RvalidKnown_A 503662787 503402351 0 0
WreadyKnown_A 503662787 503402351 0 0
gen_passthru_fifo.paramCheckPass 2852 2852 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 1604322 0 0
T1 490926 526 0 0
T2 9603 47 0 0
T3 688610 29886 0 0
T4 244181 4755 0 0
T5 384882 0 0 0
T6 237679 0 0 0
T29 16981 12 0 0
T30 7662 0 0 0
T31 17144 92 0 0
T34 0 9 0 0
T35 7736 0 0 0
T51 0 75 0 0
T86 0 74 0 0
T87 0 16 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2852 2852 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T35 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 503662787 31397747 0 0
DepthKnown_A 503662787 503402351 0 0
RvalidKnown_A 503662787 503402351 0 0
WreadyKnown_A 503662787 503402351 0 0
gen_passthru_fifo.paramCheckPass 2852 2852 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 31397747 0 0
T1 490926 2243 0 0
T2 9603 12 0 0
T3 688610 1232 0 0
T4 244181 6267 0 0
T5 384882 53587 0 0
T6 237679 115606 0 0
T29 16981 34 0 0
T30 7662 13 0 0
T31 17144 60 0 0
T35 7736 11 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2852 2852 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T35 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 503662787 40626371 0 0
DepthKnown_A 503662787 503402351 0 0
RvalidKnown_A 503662787 503402351 0 0
WreadyKnown_A 503662787 503402351 0 0
gen_passthru_fifo.paramCheckPass 2852 2852 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 40626371 0 0
T1 490926 2243 0 0
T2 9603 58 0 0
T3 688610 5934 0 0
T4 244181 19325 0 0
T5 384882 53587 0 0
T6 237679 115606 0 0
T29 16981 34 0 0
T30 7662 56 0 0
T31 17144 224 0 0
T35 7736 11 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 503662787 503402351 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 2852 2852 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T29 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T35 1 1 0 0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T29
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 501774998 1567321 0 0
DepthKnown_A 501774998 501569118 0 0
RvalidKnown_A 501774998 501569118 0 0
WreadyKnown_A 501774998 501569118 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 501774998 1567321 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 1567321 0 0
T1 490926 526 0 0
T2 9603 47 0 0
T3 688610 29886 0 0
T4 244181 4755 0 0
T5 384882 0 0 0
T6 237679 0 0 0
T29 16981 12 0 0
T30 7662 0 0 0
T31 17144 92 0 0
T34 0 9 0 0
T35 7736 0 0 0
T51 0 75 0 0
T86 0 74 0 0
T87 0 16 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 1567321 0 0
T1 490926 526 0 0
T2 9603 47 0 0
T3 688610 29886 0 0
T4 244181 4755 0 0
T5 384882 0 0 0
T6 237679 0 0 0
T29 16981 12 0 0
T30 7662 0 0 0
T31 17144 92 0 0
T34 0 9 0 0
T35 7736 0 0 0
T51 0 75 0 0
T86 0 74 0 0
T87 0 16 0 0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
TotalCoveredPercent
Conditions161062.50
Logical161062.50
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 501774998 577123 0 0
DepthKnown_A 501774998 501569118 0 0
RvalidKnown_A 501774998 501569118 0 0
WreadyKnown_A 501774998 501569118 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 501774998 577123 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 577123 0 0
T1 490926 162 0 0
T2 9603 14 0 0
T3 688610 3844 0 0
T4 244181 0 0 0
T5 384882 0 0 0
T6 237679 0 0 0
T29 16981 12 0 0
T30 7662 0 0 0
T31 17144 35 0 0
T34 0 9 0 0
T35 7736 0 0 0
T43 0 16160 0 0
T51 0 7 0 0
T86 0 16 0 0
T87 0 16 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 577123 0 0
T1 490926 162 0 0
T2 9603 14 0 0
T3 688610 3844 0 0
T4 244181 0 0 0
T5 384882 0 0 0
T6 237679 0 0 0
T29 16981 12 0 0
T30 7662 0 0 0
T31 17144 35 0 0
T34 0 9 0 0
T35 7736 0 0 0
T43 0 16160 0 0
T51 0 7 0 0
T86 0 16 0 0
T87 0 16 0 0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T31
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T29
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT2,T3,T31
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 501774998 1115259 0 0
DepthKnown_A 501774998 501569118 0 0
RvalidKnown_A 501774998 501569118 0 0
WreadyKnown_A 501774998 501569118 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 501774998 1115259 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 1115259 0 0
T1 490926 162 0 0
T2 9603 47 0 0
T3 688610 17276 0 0
T4 244181 0 0 0
T5 384882 0 0 0
T6 237679 0 0 0
T29 16981 12 0 0
T30 7662 0 0 0
T31 17144 92 0 0
T34 0 9 0 0
T35 7736 0 0 0
T43 0 72522 0 0
T51 0 29 0 0
T86 0 74 0 0
T87 0 16 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 501569118 0 0
T1 490926 490841 0 0
T2 9603 9512 0 0
T3 688610 688550 0 0
T4 244181 244107 0 0
T5 384882 384820 0 0
T6 237679 237610 0 0
T29 16981 16907 0 0
T30 7662 7603 0 0
T31 17144 17090 0 0
T35 7736 7644 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 501774998 1115259 0 0
T1 490926 162 0 0
T2 9603 47 0 0
T3 688610 17276 0 0
T4 244181 0 0 0
T5 384882 0 0 0
T6 237679 0 0 0
T29 16981 12 0 0
T30 7662 0 0 0
T31 17144 92 0 0
T34 0 9 0 0
T35 7736 0 0 0
T43 0 72522 0 0
T51 0 29 0 0
T86 0 74 0 0
T87 0 16 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%