Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14773353	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	15563583	1		T1	5		T2	23		T3	13154

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29721066	1		T1	4		T2	13		T3	25718
values[0x0]	307535	1		T1	6		T2	8		T3	170
values[0x1]	308335	1		T1	3		T2	13		T3	186

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11778060	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	18558876	1		T1	8		T2	24		T3	15709

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	90522	1		T3	91		T4	364		T21	7
valid_sources[0x01]	158324	1		T3	84		T4	340		T82	311
valid_sources[0x02]	90895	1		T3	73		T4	342		T21	4
valid_sources[0x03]	89661	1		T3	117		T6	1		T4	350
valid_sources[0x04]	187556	1		T3	105		T6	2		T4	358
valid_sources[0x05]	188813	1		T3	131		T6	1		T19	1
valid_sources[0x06]	144423	1		T3	102		T6	3		T4	335
valid_sources[0x07]	89111	1		T3	94		T6	1		T4	387
valid_sources[0x08]	91318	1		T3	126		T4	323		T21	8
valid_sources[0x09]	88897	1		T3	90		T4	341		T21	8
valid_sources[0x0a]	87539	1		T3	85		T6	1		T4	339
valid_sources[0x0b]	211728	1		T3	86		T26	1		T4	322
valid_sources[0x0c]	137713	1		T3	102		T6	1		T4	334
valid_sources[0x0d]	110944	1		T3	112		T6	2		T4	355
valid_sources[0x0e]	89010	1		T3	140		T6	4		T4	323
valid_sources[0x0f]	88500	1		T3	104		T4	364		T21	14
valid_sources[0x10]	89958	1		T3	110		T4	369		T21	2
valid_sources[0x11]	108398	1		T3	100		T26	1		T6	2
valid_sources[0x12]	114078	1		T3	91		T4	353		T21	3
valid_sources[0x13]	88084	1		T3	77		T4	345		T21	9
valid_sources[0x14]	89125	1		T3	93		T6	2		T4	351
valid_sources[0x15]	86969	1		T3	134		T6	1		T16	1
valid_sources[0x16]	119185	1		T1	1		T3	106		T6	3
valid_sources[0x17]	121883	1		T3	84		T6	1		T4	349
valid_sources[0x18]	189587	1		T3	119		T4	379		T21	8
valid_sources[0x19]	90689	1		T3	97		T6	4		T16	1
valid_sources[0x1a]	96493	1		T3	71		T4	351		T21	8
valid_sources[0x1b]	164686	1		T3	102		T4	336		T21	7
valid_sources[0x1c]	222160	1		T3	108		T6	1		T4	316
valid_sources[0x1d]	87575	1		T3	84		T6	5		T4	340
valid_sources[0x1e]	113114	1		T3	127		T26	1		T4	324
valid_sources[0x1f]	224508	1		T3	93		T4	322		T21	9
valid_sources[0x20]	87795	1		T3	104		T6	1		T4	327
valid_sources[0x21]	93622	1		T3	93		T6	4		T16	1
valid_sources[0x22]	236082	1		T3	113		T4	322		T21	6
valid_sources[0x23]	90310	1		T3	125		T6	3		T19	1
valid_sources[0x24]	88196	1		T3	86		T6	3		T4	355
valid_sources[0x25]	88337	1		T3	95		T4	349		T21	6
valid_sources[0x26]	93530	1		T1	1		T3	101		T26	1
valid_sources[0x27]	89055	1		T3	84		T4	339		T21	11
valid_sources[0x28]	145795	1		T3	121		T4	347		T21	3
valid_sources[0x29]	87553	1		T3	110		T17	16		T4	361
valid_sources[0x2a]	88438	1		T3	85		T6	2		T4	372
valid_sources[0x2b]	112967	1		T3	130		T6	3		T4	332
valid_sources[0x2c]	88666	1		T3	115		T19	1		T4	353
valid_sources[0x2d]	89630	1		T3	105		T6	1		T4	362
valid_sources[0x2e]	89370	1		T3	118		T6	1		T17	7
valid_sources[0x2f]	88930	1		T3	107		T4	358		T21	5
valid_sources[0x30]	100977	1		T3	105		T6	1		T4	346
valid_sources[0x31]	91503	1		T3	92		T26	1		T4	375
valid_sources[0x32]	89034	1		T3	79		T4	336		T21	9
valid_sources[0x33]	90814	1		T3	113		T6	2		T4	333
valid_sources[0x34]	88824	1		T3	109		T4	316		T21	2
valid_sources[0x35]	237318	1		T3	88		T6	1		T16	1
valid_sources[0x36]	140458	1		T3	84		T6	1		T4	381
valid_sources[0x37]	88485	1		T3	90		T6	3		T4	352
valid_sources[0x38]	150404	1		T3	132		T4	298		T21	8
valid_sources[0x39]	152762	1		T3	102		T6	2		T4	356
valid_sources[0x3a]	88871	1		T3	111		T6	1		T4	323
valid_sources[0x3b]	89281	1		T3	128		T4	338		T21	12
valid_sources[0x3c]	89905	1		T3	65		T6	1		T4	302
valid_sources[0x3d]	89991	1		T1	1		T3	93		T6	3
valid_sources[0x3e]	89913	1		T3	127		T6	1		T4	363
valid_sources[0x3f]	115539	1		T3	105		T6	1		T18	4
valid_sources[0x40]	364702	1		T3	95		T6	3		T4	310
valid_sources[0x41]	88153	1		T3	102		T16	1		T4	335
valid_sources[0x42]	87788	1		T3	108		T17	65		T4	371
valid_sources[0x43]	87897	1		T3	110		T6	2		T4	335
valid_sources[0x44]	88441	1		T3	93		T4	335		T21	8
valid_sources[0x45]	162832	1		T3	95		T4	337		T21	14
valid_sources[0x46]	140981	1		T3	105		T16	1		T4	368
valid_sources[0x47]	118837	1		T3	79		T6	3		T4	345
valid_sources[0x48]	89391	1		T3	104		T6	4		T4	363
valid_sources[0x49]	90016	1		T3	113		T4	310		T21	7
valid_sources[0x4a]	155760	1		T3	91		T6	1		T4	350
valid_sources[0x4b]	118474	1		T3	113		T4	376		T21	10
valid_sources[0x4c]	88342	1		T3	115		T6	2		T4	330
valid_sources[0x4d]	426698	1		T3	68		T4	322		T21	7
valid_sources[0x4e]	267477	1		T3	88		T4	365		T21	3
valid_sources[0x4f]	89712	1		T3	94		T6	1		T4	307
valid_sources[0x50]	87456	1		T3	75		T6	2		T4	384
valid_sources[0x51]	90119	1		T3	96		T26	1		T6	1
valid_sources[0x52]	166388	1		T3	98		T4	334		T21	10
valid_sources[0x53]	88829	1		T3	109		T6	1		T4	346
valid_sources[0x54]	87337	1		T3	109		T6	1		T16	1
valid_sources[0x55]	86692	1		T3	94		T6	1		T4	354
valid_sources[0x56]	88693	1		T3	91		T6	2		T4	310
valid_sources[0x57]	88117	1		T3	87		T6	2		T4	376
valid_sources[0x58]	87057	1		T3	124		T6	1		T4	314
valid_sources[0x59]	89994	1		T3	90		T6	5		T4	344
valid_sources[0x5a]	237414	1		T3	117		T4	313		T21	9
valid_sources[0x5b]	88815	1		T3	83		T6	1		T4	303
valid_sources[0x5c]	88483	1		T3	76		T4	324		T21	7
valid_sources[0x5d]	89574	1		T3	116		T6	2		T16	2
valid_sources[0x5e]	108716	1		T3	107		T6	1		T4	306
valid_sources[0x5f]	88712	1		T3	105		T4	331		T21	11
valid_sources[0x60]	160343	1		T3	93		T4	332		T21	3
valid_sources[0x61]	243209	1		T3	114		T4	313		T21	3
valid_sources[0x62]	214349	1		T3	90		T4	357		T21	5
valid_sources[0x63]	88268	1		T3	94		T4	328		T21	5
valid_sources[0x64]	88414	1		T3	101		T6	1		T18	2
valid_sources[0x65]	87801	1		T3	111		T6	1		T17	49
valid_sources[0x66]	87782	1		T3	108		T6	3		T4	286
valid_sources[0x67]	87842	1		T3	111		T4	312		T21	3
valid_sources[0x68]	111445	1		T3	102		T4	364		T21	13
valid_sources[0x69]	116437	1		T3	106		T6	1		T4	353
valid_sources[0x6a]	104405	1		T3	119		T16	1		T4	365
valid_sources[0x6b]	89530	1		T3	118		T4	319		T21	4
valid_sources[0x6c]	88559	1		T3	103		T6	1		T20	26
valid_sources[0x6d]	185638	1		T3	93		T6	1		T4	326
valid_sources[0x6e]	109267	1		T3	141		T6	1		T4	349
valid_sources[0x6f]	89349	1		T3	77		T4	313		T21	10
valid_sources[0x70]	88533	1		T3	116		T19	1		T4	303
valid_sources[0x71]	88735	1		T3	82		T6	1		T17	73
valid_sources[0x72]	186711	1		T3	121		T6	1		T4	368
valid_sources[0x73]	237973	1		T3	101		T6	3		T4	324
valid_sources[0x74]	115370	1		T3	116		T6	1		T4	342
valid_sources[0x75]	89591	1		T3	86		T26	1		T4	338
valid_sources[0x76]	87192	1		T3	111		T6	2		T4	347
valid_sources[0x77]	120570	1		T3	108		T6	1		T4	342
valid_sources[0x78]	88727	1		T3	116		T6	2		T4	353
valid_sources[0x79]	88939	1		T3	93		T4	320		T21	12
valid_sources[0x7a]	88747	1		T1	1		T3	112		T6	1
valid_sources[0x7b]	123714	1		T3	120		T6	2		T4	338
valid_sources[0x7c]	87872	1		T3	78		T6	4		T19	1
valid_sources[0x7d]	89659	1		T3	95		T6	2		T4	370
valid_sources[0x7e]	88041	1		T1	2		T3	93		T6	2
valid_sources[0x7f]	199294	1		T3	89		T6	1		T18	3
valid_sources[0x80]	88969	1		T3	95		T4	361		T21	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15073144

1

T1

1

T2

9

T3

12903

values[0x0]

all_enables

biggest_size

252943

1

T1

3

T2

5

T3

118

values[0x1]

all_enables

biggest_size

237496

1

T1

1

T2

9

T3

133