Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14789124	1		T1	8		T2	11		T3	12920
full_word	15564726	1		T1	5		T2	23		T3	13154

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30353530	1		T1	13		T2	34		T3	26074
auto[TlIntgErrCmd]	112	1		T193	8		T195	4		T217	4
auto[TlIntgErrData]	98	1		T193	6		T195	9		T217	3
auto[TlIntgErrBoth]	110	1		T193	6		T195	7		T217	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29723173	1		T1	4		T2	13		T3	25718
auto[1]	630677	1		T1	9		T2	21		T3	356

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14649675	1		T1	3		T2	4		T3	12815
auto[TlIntgErrNone]	partial	auto[1]	139152	1		T1	5		T2	7		T3	105
auto[TlIntgErrNone]	full_word	auto[0]	15073354	1		T1	1		T2	9		T3	12903
auto[TlIntgErrNone]	full_word	auto[1]	491349	1		T1	4		T2	14		T3	251
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T193	3		T195	1		T217	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1		T193	5		T195	3		T217	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T304	1		T305	1		T306	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T307	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	43	1		T193	2		T195	4		T217	1
auto[TlIntgErrData]	partial	auto[1]	45	1		T193	3		T195	2		T217	2
auto[TlIntgErrData]	full_word	auto[0]	7	1		T193	1		T195	2		T301	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T195	1		T303	1		T308	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1		T193	1		T195	5		T217	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1		T193	5		T195	2		T217	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T300	1		T305	1		T308	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T301	1		T309	1		T306	1