Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	508824808	12303	0	0
ep_in_enable_rd_A	508824808	4134	0	0
ep_out_enable_rd_A	508824808	4492	0	0
in_iso_rd_A	508824808	4086	0	0
intr_enable_rd_A	508824808	6441	0	0
out_iso_rd_A	508824808	4404	0	0
phy_config_rd_A	508824808	2660	0	0
phy_pins_drive_rd_A	508824808	3510	0	0
rxenable_setup_rd_A	508824808	3758	0	0
set_nak_out_rd_A	508824808	4489	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508824808	12303	0	0
T193	51129	3	0	0
T194	8966	12	0	0
T195	53822	10	0	0
T211	8440	448	0	0
T212	6023	8	0	0
T217	17266	2	0	0
T218	4394	14	0	0
T238	6578	12	0	0
T239	3939	15	0	0
T240	9726	14	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508824808	4134	0	0
T194	8966	69	0	0
T195	53822	504	0	0
T212	6023	6	0	0
T238	6578	9	0	0
T240	9726	17	0	0
T258	2791	8	0	0
T262	5111	9	0	0
T270	9156	59	0	0
T273	5700	10	0	0
T281	10634	85	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508824808	4492	0	0
T194	8966	107	0	0
T195	53822	495	0	0
T212	6023	52	0	0
T238	6578	22	0	0
T240	9726	72	0	0
T262	5111	9	0	0
T270	9156	40	0	0
T273	5700	7	0	0
T281	10634	115	0	0
T282	50114	548	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508824808	4086	0	0
T194	8966	13	0	0
T195	53822	452	0	0
T212	6023	8	0	0
T238	6578	26	0	0
T240	9726	9	0	0
T258	2791	41	0	0
T262	5111	37	0	0
T270	9156	12	0	0
T273	5700	41	0	0
T281	10634	94	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508824808	6441	0	0
T194	8966	24	0	0
T195	53822	619	0	0
T212	6023	4	0	0
T238	6578	31	0	0
T240	9726	95	0	0
T258	2791	6	0	0
T270	9156	34	0	0
T283	1875	21	0	0
T284	2747	23	0	0
T285	1842	19	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508824808	4404	0	0
T194	8966	92	0	0
T195	53822	496	0	0
T212	6023	10	0	0
T238	6578	2	0	0
T240	9726	19	0	0
T258	2791	6	0	0
T262	5111	5	0	0
T270	9156	63	0	0
T273	5700	20	0	0
T281	10634	96	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508824808	2660	0	0
T194	8966	54	0	0
T195	53822	332	0	0
T212	6023	25	0	0
T240	9726	42	0	0
T258	2791	22	0	0
T262	5111	27	0	0
T270	9156	20	0	0
T273	5700	22	0	0
T281	10634	70	0	0
T282	50114	248	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508824808	3510	0	0
T194	8966	39	0	0
T195	53822	344	0	0
T212	6023	28	0	0
T238	6578	5	0	0
T240	9726	85	0	0
T258	2791	29	0	0
T262	5111	7	0	0
T270	9156	62	0	0
T273	5700	22	0	0
T281	10634	127	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508824808	3758	0	0
T194	8966	45	0	0
T195	53822	342	0	0
T212	6023	45	0	0
T238	6578	4	0	0
T240	9726	69	0	0
T262	5111	40	0	0
T270	9156	20	0	0
T273	5700	45	0	0
T281	10634	93	0	0
T282	50114	342	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508824808	4489	0	0
T194	8966	43	0	0
T195	53822	400	0	0
T212	6023	17	0	0
T238	6578	36	0	0
T240	9726	56	0	0
T258	2791	53	0	0
T262	5111	108	0	0
T270	9156	60	0	0
T281	10634	78	0	0
T282	50114	584	0	0