Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16436881	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	17244596	1		T1	3		T2	12009		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	33049689	1		T1	3		T2	23374		T3	2
values[0x0]	316233	1		T1	5		T2	263		T3	5
values[0x1]	315555	1		T1	2		T2	262		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13106473	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20575004	1		T1	4		T2	14413		T3	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	101259	1		T2	251		T4	80		T5	93
valid_sources[0x01]	102745	1		T2	180		T4	94		T5	105
valid_sources[0x02]	104495	1		T2	306		T4	97		T5	89
valid_sources[0x03]	147252	1		T2	6		T4	85		T5	93
valid_sources[0x04]	100944	1		T2	110		T4	80		T5	101
valid_sources[0x05]	99689	1		T2	29		T4	106		T5	93
valid_sources[0x06]	101894	1		T2	36		T4	79		T5	118
valid_sources[0x07]	250025	1		T2	231		T27	9		T4	89
valid_sources[0x08]	101561	1		T2	215		T4	85		T5	102
valid_sources[0x09]	101433	1		T2	55		T4	94		T5	102
valid_sources[0x0a]	101496	1		T2	36		T4	70		T5	98
valid_sources[0x0b]	106772	1		T2	122		T4	87		T5	92
valid_sources[0x0c]	102282	1		T2	67		T4	94		T5	110
valid_sources[0x0d]	101435	1		T2	98		T4	74		T5	108
valid_sources[0x0e]	100730	1		T2	25		T27	1		T4	99
valid_sources[0x0f]	100770	1		T2	20		T4	86		T5	87
valid_sources[0x10]	101940	1		T2	145		T4	99		T5	105
valid_sources[0x11]	99398	1		T1	10		T2	104		T4	100
valid_sources[0x12]	99996	1		T2	74		T4	95		T5	96
valid_sources[0x13]	104251	1		T2	5		T4	69		T5	88
valid_sources[0x14]	101248	1		T2	23		T4	83		T5	107
valid_sources[0x15]	101237	1		T2	61		T4	104		T5	120
valid_sources[0x16]	100601	1		T2	36		T4	79		T5	122
valid_sources[0x17]	102604	1		T2	122		T4	97		T5	90
valid_sources[0x18]	278960	1		T2	97		T29	3		T4	99
valid_sources[0x19]	102055	1		T2	231		T4	78		T5	80
valid_sources[0x1a]	120612	1		T2	148		T4	91		T5	117
valid_sources[0x1b]	100262	1		T4	88		T5	134		T30	9
valid_sources[0x1c]	101482	1		T2	149		T4	98		T5	90
valid_sources[0x1d]	118484	1		T2	17		T4	82		T5	89
valid_sources[0x1e]	121387	1		T2	207		T4	98		T5	81
valid_sources[0x1f]	101924	1		T2	57		T4	107		T5	114
valid_sources[0x20]	233001	1		T2	22		T4	77		T5	110
valid_sources[0x21]	100569	1		T2	302		T4	98		T5	121
valid_sources[0x22]	101278	1		T2	16		T4	103		T5	87
valid_sources[0x23]	135125	1		T2	66		T4	89		T5	96
valid_sources[0x24]	101527	1		T2	21		T3	10		T4	96
valid_sources[0x25]	99838	1		T2	96		T4	71		T5	89
valid_sources[0x26]	101192	1		T2	122		T4	81		T5	109
valid_sources[0x27]	100931	1		T2	3		T27	4		T4	77
valid_sources[0x28]	129240	1		T2	52		T4	102		T5	124
valid_sources[0x29]	99182	1		T2	4		T4	83		T5	93
valid_sources[0x2a]	100990	1		T2	295		T4	87		T5	94
valid_sources[0x2b]	118849	1		T2	192		T4	90		T5	100
valid_sources[0x2c]	123408	1		T2	184		T4	104		T5	105
valid_sources[0x2d]	224275	1		T2	129		T4	87		T5	99
valid_sources[0x2e]	101949	1		T2	281		T4	86		T5	105
valid_sources[0x2f]	180862	1		T2	249		T4	100		T5	108
valid_sources[0x30]	101814	1		T2	179		T4	81		T5	90
valid_sources[0x31]	211677	1		T2	152		T4	79		T5	98
valid_sources[0x32]	100860	1		T2	85		T4	73		T5	88
valid_sources[0x33]	101302	1		T2	142		T27	4		T4	70
valid_sources[0x34]	99490	1		T4	95		T5	83		T30	8
valid_sources[0x35]	348614	1		T2	78		T4	68		T5	96
valid_sources[0x36]	125918	1		T2	146		T4	98		T5	101
valid_sources[0x37]	100241	1		T2	229		T4	64		T5	92
valid_sources[0x38]	100799	1		T2	29		T4	85		T5	98
valid_sources[0x39]	100482	1		T2	14		T4	73		T5	81
valid_sources[0x3a]	102165	1		T2	33		T4	71		T5	107
valid_sources[0x3b]	101103	1		T2	69		T4	86		T5	113
valid_sources[0x3c]	101961	1		T2	72		T29	2		T4	68
valid_sources[0x3d]	101962	1		T2	118		T4	74		T5	94
valid_sources[0x3e]	242270	1		T2	135		T4	67		T5	97
valid_sources[0x3f]	100659	1		T2	67		T4	78		T5	100
valid_sources[0x40]	143045	1		T2	7		T4	87		T5	94
valid_sources[0x41]	102995	1		T2	91		T27	1		T4	113
valid_sources[0x42]	99790	1		T2	14		T4	104		T5	108
valid_sources[0x43]	103487	1		T2	12		T4	99		T5	115
valid_sources[0x44]	145914	1		T2	23		T4	95		T5	92
valid_sources[0x45]	101916	1		T2	84		T4	87		T5	90
valid_sources[0x46]	101416	1		T2	203		T4	66		T5	96
valid_sources[0x47]	126268	1		T4	88		T5	107		T30	6
valid_sources[0x48]	100439	1		T2	140		T4	106		T5	111
valid_sources[0x49]	106366	1		T2	21		T4	74		T5	91
valid_sources[0x4a]	406871	1		T2	209		T4	110		T5	99
valid_sources[0x4b]	101016	1		T2	21		T4	81		T5	90
valid_sources[0x4c]	104530	1		T2	28		T4	83		T5	104
valid_sources[0x4d]	194791	1		T2	45		T4	83		T5	103
valid_sources[0x4e]	101336	1		T2	119		T4	89		T5	101
valid_sources[0x4f]	101071	1		T2	226		T4	88		T5	83
valid_sources[0x50]	101221	1		T2	87		T4	88		T5	85
valid_sources[0x51]	100706	1		T2	2		T4	80		T5	105
valid_sources[0x52]	101978	1		T2	72		T4	96		T5	96
valid_sources[0x53]	232745	1		T2	158		T4	97		T5	98
valid_sources[0x54]	102448	1		T2	33		T4	89		T5	120
valid_sources[0x55]	105085	1		T4	81		T5	87		T30	14
valid_sources[0x56]	154199	1		T2	35		T4	94		T5	95
valid_sources[0x57]	99658	1		T2	122		T4	68		T5	100
valid_sources[0x58]	102208	1		T2	270		T4	86		T5	109
valid_sources[0x59]	103088	1		T2	24		T4	88		T5	113
valid_sources[0x5a]	100308	1		T2	105		T4	107		T5	95
valid_sources[0x5b]	100077	1		T4	73		T5	107		T30	8
valid_sources[0x5c]	153847	1		T2	81		T4	90		T5	81
valid_sources[0x5d]	102752	1		T2	7		T4	103		T5	85
valid_sources[0x5e]	249581	1		T2	172		T4	77		T5	108
valid_sources[0x5f]	213837	1		T2	12		T4	86		T5	114
valid_sources[0x60]	101522	1		T2	94		T32	10		T4	80
valid_sources[0x61]	100107	1		T2	95		T4	75		T5	95
valid_sources[0x62]	101882	1		T2	206		T4	90		T5	104
valid_sources[0x63]	118732	1		T2	220		T4	104		T5	102
valid_sources[0x64]	378424	1		T2	26		T4	81		T5	102
valid_sources[0x65]	132609	1		T2	5		T4	90		T5	105
valid_sources[0x66]	102359	1		T2	14		T4	84		T5	104
valid_sources[0x67]	147175	1		T2	237		T4	63		T5	104
valid_sources[0x68]	101524	1		T2	69		T4	95		T5	102
valid_sources[0x69]	99976	1		T2	39		T4	78		T5	109
valid_sources[0x6a]	103132	1		T2	41		T4	81		T5	104
valid_sources[0x6b]	153379	1		T2	70		T4	79		T5	101
valid_sources[0x6c]	102820	1		T2	23		T4	84		T5	104
valid_sources[0x6d]	99791	1		T2	96		T27	1		T4	79
valid_sources[0x6e]	100468	1		T2	75		T4	90		T5	102
valid_sources[0x6f]	101822	1		T2	74		T29	4		T4	88
valid_sources[0x70]	101530	1		T2	49		T4	86		T5	98
valid_sources[0x71]	101348	1		T2	21		T4	89		T5	137
valid_sources[0x72]	101049	1		T2	103		T4	110		T5	90
valid_sources[0x73]	100545	1		T2	24		T4	109		T5	115
valid_sources[0x74]	131081	1		T4	95		T5	91		T30	10
valid_sources[0x75]	105986	1		T2	81		T4	85		T5	95
valid_sources[0x76]	100594	1		T2	96		T4	88		T5	86
valid_sources[0x77]	101616	1		T2	149		T4	78		T5	109
valid_sources[0x78]	101535	1		T2	73		T4	78		T5	93
valid_sources[0x79]	102990	1		T2	25		T4	74		T5	98
valid_sources[0x7a]	236484	1		T2	176		T4	93		T5	96
valid_sources[0x7b]	103140	1		T2	7		T4	89		T5	127
valid_sources[0x7c]	398621	1		T2	64		T4	80		T5	88
valid_sources[0x7d]	100622	1		T2	84		T4	90		T5	117
valid_sources[0x7e]	100766	1		T2	115		T4	90		T5	113
valid_sources[0x7f]	101133	1		T2	77		T4	79		T5	88
valid_sources[0x80]	100176	1		T4	96		T5	84		T30	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16739869

1

T2

11651

T3

1

T27

3

values[0x0]

all_enables

biggest_size

260827

1

T1

3

T2

188

T3

5

values[0x1]

all_enables

biggest_size

243900

1

T2

170

T27

3

T28

2