Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	16453745	1		T1	7		T2	11890		T3	4
full_word	17245733	1		T1	3		T2	12009		T3	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33699198	1		T1	10		T2	23899		T3	10
auto[TlIntgErrCmd]	93	1		T175	8		T203	6		T206	10
auto[TlIntgErrData]	97	1		T175	7		T203	2		T206	7
auto[TlIntgErrBoth]	90	1		T175	5		T203	2		T206	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33051862	1		T1	3		T2	23374		T3	2
auto[1]	647616	1		T1	7		T2	525		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16311645	1		T1	3		T2	11723		T3	1
auto[TlIntgErrNone]	partial	auto[1]	141844	1		T1	4		T2	167		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	16740075	1		T2	11651		T3	1		T27	3
auto[TlIntgErrNone]	full_word	auto[1]	505634	1		T1	3		T2	358		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T175	3		T203	4		T206	3
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T175	3		T203	2		T206	7
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T175	1		T272	1		T273	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T175	1		T268	1		-	-
auto[TlIntgErrData]	partial	auto[0]	51	1		T175	2		T203	1		T206	3
auto[TlIntgErrData]	partial	auto[1]	39	1		T175	5		T203	1		T206	3
auto[TlIntgErrData]	full_word	auto[0]	3	1		T206	1		T274	1		T275	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T222	2		T270	1		T273	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1		T175	3		T203	1		T206	1
auto[TlIntgErrBoth]	partial	auto[1]	38	1		T175	2		T203	1		T206	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T222	2		T268	1		T276	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T206	1		T219	1		T277	1