Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.73	97.53	86.57	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	509365877	12699	0	0
ep_in_enable_rd_A	509365877	3211	0	0
ep_out_enable_rd_A	509365877	3377	0	0
in_iso_rd_A	509365877	3182	0	0
intr_enable_rd_A	509365877	4501	0	0
out_iso_rd_A	509365877	3608	0	0
phy_config_rd_A	509365877	1868	0	0
phy_pins_drive_rd_A	509365877	2737	0	0
rxenable_setup_rd_A	509365877	3209	0	0
set_nak_out_rd_A	509365877	3251	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	12699	0	0
T175	26325	4	0	0
T176	8070	21	0	0
T177	3302	4	0	0
T202	6331	286	0	0
T203	49333	4	0	0
T206	47219	2	0	0
T207	13092	14	0	0
T208	13936	985	0	0
T209	14537	803	0	0
T216	9236	15	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	3211	0	0
T203	49333	116	0	0
T204	5890	13	0	0
T206	47219	511	0	0
T216	9236	116	0	0
T222	51475	704	0	0
T229	41433	145	0	0
T230	4823	2	0	0
T232	4228	50	0	0
T235	3393	6	0	0
T248	7838	61	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	3377	0	0
T178	9952	40	0	0
T203	49333	225	0	0
T204	5890	32	0	0
T206	47219	568	0	0
T216	9236	50	0	0
T222	51475	590	0	0
T229	41433	104	0	0
T230	4823	28	0	0
T232	4228	94	0	0
T235	3393	20	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	3182	0	0
T178	9952	15	0	0
T203	49333	282	0	0
T204	5890	9	0	0
T206	47219	505	0	0
T216	9236	57	0	0
T222	51475	555	0	0
T229	41433	179	0	0
T230	4823	7	0	0
T232	4228	32	0	0
T235	3393	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	4501	0	0
T178	9952	9	0	0
T203	49333	287	0	0
T204	5890	23	0	0
T206	47219	659	0	0
T216	9236	13	0	0
T222	51475	625	0	0
T229	41433	124	0	0
T230	4823	107	0	0
T232	4228	2	0	0
T249	2640	12	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	3608	0	0
T178	9952	3	0	0
T203	49333	253	0	0
T204	5890	8	0	0
T206	47219	708	0	0
T216	9236	123	0	0
T222	51475	519	0	0
T229	41433	148	0	0
T230	4823	5	0	0
T232	4228	45	0	0
T235	3393	69	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	1868	0	0
T178	9952	8	0	0
T203	49333	80	0	0
T206	47219	294	0	0
T216	9236	48	0	0
T222	51475	310	0	0
T229	41433	141	0	0
T230	4823	10	0	0
T232	4228	37	0	0
T235	3393	21	0	0
T248	7838	36	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	2737	0	0
T178	9952	4	0	0
T203	49333	112	0	0
T204	5890	8	0	0
T206	47219	401	0	0
T216	9236	13	0	0
T222	51475	322	0	0
T229	41433	124	0	0
T230	4823	10	0	0
T232	4228	7	0	0
T248	7838	77	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	3209	0	0
T178	9952	6	0	0
T203	49333	337	0	0
T204	5890	3	0	0
T206	47219	583	0	0
T216	9236	68	0	0
T222	51475	444	0	0
T229	41433	150	0	0
T230	4823	11	0	0
T232	4228	53	0	0
T235	3393	49	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	3251	0	0
T178	9952	17	0	0
T203	49333	245	0	0
T204	5890	9	0	0
T206	47219	382	0	0
T216	9236	91	0	0
T222	51475	480	0	0
T229	41433	119	0	0
T232	4228	44	0	0
T235	3393	3	0	0
T248	7838	47	0	0