Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.73	97.53	86.57	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	88.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.73	97.53	86.57	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.73	97.53	86.57	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.43	98.59	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.43	98.59	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.43	98.59	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T5

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	507496517	142560610	0	0
DepthKnown_A	507496517	507289217	0	0
RvalidKnown_A	507496517	507289217	0	0
WreadyKnown_A	507496517	507289217	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	507496517	142560610	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	142560610	0	0
T2	259625	251604	0	0
T3	10444	0	0	0
T4	210740	202867	0	0
T5	188523	181763	0	0
T16	0	325755	0	0
T21	0	331744	0	0
T23	0	2789	0	0
T27	161153	0	0	0
T28	9424	0	0	0
T29	7247	0	0	0
T30	561157	476589	0	0
T31	287352	280534	0	0
T32	9421	0	0	0
T44	0	573	0	0
T88	0	304980	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	142560610	0	0
T2	259625	251604	0	0
T3	10444	0	0	0
T4	210740	202867	0	0
T5	188523	181763	0	0
T16	0	325755	0	0
T21	0	331744	0	0
T23	0	2789	0	0
T27	161153	0	0	0
T28	9424	0	0	0
T29	7247	0	0	0
T30	561157	476589	0	0
T31	287352	280534	0	0
T32	9421	0	0	0
T44	0	573	0	0
T88	0	304980	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T62,T63,T64
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T2,T27,T28

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	507496517	289416339	0	0
DepthKnown_A	507496517	507289217	0	0
RvalidKnown_A	507496517	507289217	0	0
WreadyKnown_A	507496517	507289217	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	507496517	289416339	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	289416339	0	0
T1	6902	1175	0	0
T2	259625	251537	0	0
T3	10444	1304	0	0
T4	210740	202816	0	0
T5	188523	181703	0	0
T27	161153	1640	0	0
T28	9424	2379	0	0
T29	7247	1315	0	0
T30	561157	517905	0	0
T32	9421	2349	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	289416339	0	0
T1	6902	1175	0	0
T2	259625	251537	0	0
T3	10444	1304	0	0
T4	210740	202816	0	0
T5	188523	181703	0	0
T27	161153	1640	0	0
T28	9424	2379	0	0
T29	7247	1315	0	0
T30	561157	517905	0	0
T32	9421	2349	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T51,T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T27,T28

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T27,T28

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T27,T28
1	1	0	Not Covered
1	1	1	Covered	T2,T27,T28

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T27,T28
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T27,T28

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T27,T28
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	507496517	23344857	0	0
DepthKnown_A	507496517	507289217	0	0
RvalidKnown_A	507496517	507289217	0	0
WreadyKnown_A	507496517	507289217	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	507496517	23344857	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	23344857	0	0
T2	259625	5306	0	0
T3	10444	0	0	0
T4	210740	2605	0	0
T5	188523	1914	0	0
T6	0	113	0	0
T16	0	484	0	0
T17	0	19305	0	0
T27	161153	116	0	0
T28	9424	107	0	0
T29	7247	0	0	0
T30	561157	278861	0	0
T31	287352	940	0	0
T32	9421	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	23344857	0	0
T2	259625	5306	0	0
T3	10444	0	0	0
T4	210740	2605	0	0
T5	188523	1914	0	0
T6	0	113	0	0
T16	0	484	0	0
T17	0	19305	0	0
T27	161153	116	0	0
T28	9424	107	0	0
T29	7247	0	0	0
T30	561157	278861	0	0
T31	287352	940	0	0
T32	9421	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509365877	33956702	0	0
DepthKnown_A	509365877	509104522	0	0
RvalidKnown_A	509365877	509104522	0	0
WreadyKnown_A	509365877	509104522	0	0
gen_passthru_fifo.paramCheckPass	2855	2855	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	33956702	0	0
T1	6902	10	0	0
T2	259625	23899	0	0
T3	10444	10	0	0
T4	210740	22263	0	0
T5	188523	25918	0	0
T27	161153	21	0	0
T28	9424	28	0	0
T29	7247	11	0	0
T30	561157	3129	0	0
T32	9421	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2855	2855	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509365877	43682693	0	0
DepthKnown_A	509365877	509104522	0	0
RvalidKnown_A	509365877	509104522	0	0
WreadyKnown_A	509365877	509104522	0	0
gen_passthru_fifo.paramCheckPass	2855	2855	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	43682693	0	0
T1	6902	10	0	0
T2	259625	107950	0	0
T3	10444	10	0	0
T4	210740	68675	0	0
T5	188523	25918	0	0
T27	161153	95	0	0
T28	9424	28	0	0
T29	7247	11	0	0
T30	561157	3129	0	0
T32	9421	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2855	2855	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509365877	904589	0	0
DepthKnown_A	509365877	509104522	0	0
RvalidKnown_A	509365877	509104522	0	0
WreadyKnown_A	509365877	509104522	0	0
gen_passthru_fifo.paramCheckPass	2855	2855	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	904589	0	0
T4	210740	0	0	0
T5	188523	0	0	0
T6	641281	0	0	0
T16	331653	0	0	0
T17	443017	4183	0	0
T28	9424	16	0	0
T29	7247	0	0	0
T30	561157	608	0	0
T31	287352	0	0	0
T32	9421	0	0	0
T44	0	15	0	0
T80	0	13920	0	0
T82	0	10188	0	0
T83	0	938	0	0
T84	0	100	0	0
T85	0	542	0	0
T86	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2855	2855	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509365877	1879456	0	0
DepthKnown_A	509365877	509104522	0	0
RvalidKnown_A	509365877	509104522	0	0
WreadyKnown_A	509365877	509104522	0	0
gen_passthru_fifo.paramCheckPass	2855	2855	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	1879456	0	0
T4	210740	0	0	0
T5	188523	0	0	0
T6	641281	0	0	0
T16	331653	0	0	0
T17	443017	19079	0	0
T28	9424	16	0	0
T29	7247	0	0	0
T30	561157	608	0	0
T31	287352	0	0	0
T32	9421	0	0	0
T44	0	15	0	0
T80	0	62633	0	0
T82	0	10188	0	0
T83	0	938	0	0
T84	0	100	0	0
T85	0	542	0	0
T86	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2855	2855	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509365877	32984304	0	0
DepthKnown_A	509365877	509104522	0	0
RvalidKnown_A	509365877	509104522	0	0
WreadyKnown_A	509365877	509104522	0	0
gen_passthru_fifo.paramCheckPass	2855	2855	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	32984304	0	0
T1	6902	10	0	0
T2	259625	23899	0	0
T3	10444	10	0	0
T4	210740	22263	0	0
T5	188523	25918	0	0
T27	161153	21	0	0
T28	9424	12	0	0
T29	7247	11	0	0
T30	561157	2521	0	0
T32	9421	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2855	2855	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	509365877	41803237	0	0
DepthKnown_A	509365877	509104522	0	0
RvalidKnown_A	509365877	509104522	0	0
WreadyKnown_A	509365877	509104522	0	0
gen_passthru_fifo.paramCheckPass	2855	2855	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	41803237	0	0
T1	6902	10	0	0
T2	259625	107950	0	0
T3	10444	10	0	0
T4	210740	68675	0	0
T5	188523	25918	0	0
T27	161153	95	0	0
T28	9424	12	0	0
T29	7247	11	0	0
T30	561157	2521	0	0
T32	9421	10	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	509365877	509104522	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2855	2855	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T32	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T30,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T28,T30,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T28,T30,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T28,T30,T17
1	1	0	Not Covered
1	1	1	Covered	T28,T30,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T28,T30,T17
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T28,T30,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T28,T30,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	507496517	1810495	0	0
DepthKnown_A	507496517	507289217	0	0
RvalidKnown_A	507496517	507289217	0	0
WreadyKnown_A	507496517	507289217	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	507496517	1810495	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	1810495	0	0
T4	210740	0	0	0
T5	188523	0	0	0
T6	641281	0	0	0
T16	331653	0	0	0
T17	443017	19079	0	0
T28	9424	16	0	0
T29	7247	0	0	0
T30	561157	608	0	0
T31	287352	0	0	0
T32	9421	0	0	0
T44	0	15	0	0
T80	0	62633	0	0
T82	0	10188	0	0
T83	0	938	0	0
T84	0	100	0	0
T85	0	542	0	0
T86	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	1810495	0	0
T4	210740	0	0	0
T5	188523	0	0	0
T6	641281	0	0	0
T16	331653	0	0	0
T17	443017	19079	0	0
T28	9424	16	0	0
T29	7247	0	0	0
T30	561157	608	0	0
T31	287352	0	0	0
T32	9421	0	0	0
T44	0	15	0	0
T80	0	62633	0	0
T82	0	10188	0	0
T83	0	938	0	0
T84	0	100	0	0
T85	0	542	0	0
T86	0	12	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T30,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T28,T30,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T28,T30,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T28,T30,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T28,T30,T17
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T28,T30,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T28,T30,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	507496517	603828	0	0
DepthKnown_A	507496517	507289217	0	0
RvalidKnown_A	507496517	507289217	0	0
WreadyKnown_A	507496517	507289217	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	507496517	603828	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	603828	0	0
T4	210740	0	0	0
T5	188523	0	0	0
T6	641281	0	0	0
T16	331653	0	0	0
T17	443017	2435	0	0
T28	9424	16	0	0
T29	7247	0	0	0
T30	561157	194	0	0
T31	287352	0	0	0
T32	9421	0	0	0
T44	0	9	0	0
T80	0	13920	0	0
T82	0	6264	0	0
T83	0	374	0	0
T84	0	100	0	0
T85	0	126	0	0
T87	0	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	603828	0	0
T4	210740	0	0	0
T5	188523	0	0	0
T6	641281	0	0	0
T16	331653	0	0	0
T17	443017	2435	0	0
T28	9424	16	0	0
T29	7247	0	0	0
T30	561157	194	0	0
T31	287352	0	0	0
T32	9421	0	0	0
T44	0	9	0	0
T80	0	13920	0	0
T82	0	6264	0	0
T83	0	374	0	0
T84	0	100	0	0
T85	0	126	0	0
T87	0	112	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T80,T81
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T28,T30,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T28,T30,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T28,T30,T17
1	1	0	Not Covered
1	1	1	Covered	T28,T30,T17

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T30,T17

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T28,T30,T17

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T80,T81
1	0	Covered	T28,T30,T17
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T28,T30,T17
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T30,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T28,T30,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T28,T30,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	507496517	1360815	0	0
DepthKnown_A	507496517	507289217	0	0
RvalidKnown_A	507496517	507289217	0	0
WreadyKnown_A	507496517	507289217	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	507496517	1360815	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	1360815	0	0
T4	210740	0	0	0
T5	188523	0	0	0
T6	641281	0	0	0
T16	331653	0	0	0
T17	443017	10955	0	0
T28	9424	16	0	0
T29	7247	0	0	0
T30	561157	194	0	0
T31	287352	0	0	0
T32	9421	0	0	0
T44	0	9	0	0
T80	0	62633	0	0
T82	0	6264	0	0
T83	0	374	0	0
T84	0	100	0	0
T85	0	126	0	0
T87	0	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	1360815	0	0
T4	210740	0	0	0
T5	188523	0	0	0
T6	641281	0	0	0
T16	331653	0	0	0
T17	443017	10955	0	0
T28	9424	16	0	0
T29	7247	0	0	0
T30	561157	194	0	0
T31	287352	0	0	0
T32	9421	0	0	0
T44	0	9	0	0
T80	0	62633	0	0
T82	0	6264	0	0
T83	0	374	0	0
T84	0	100	0	0
T85	0	126	0	0
T87	0	112	0	0