Unified Coverage Report :: Module :: usb_fs_nb_out_pe

Module : usb_fs_nb_out_pe

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.42	96.85	90.30		87.50	92.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe	93.42	96.85	90.30		87.50	92.45	100.00

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.42	96.85	90.30		87.50	92.45	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.42	96.85	90.30		87.50	92.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_usb_fs_nb_pe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_nb_out_pe

	Line No.	Total	Covered	Percent
TOTAL		127	123	96.85
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	176	1	1	100.00
CONT_ASSIGN	178	1	1	100.00
ALWAYS	184	6	6	100.00
ALWAYS	196	4	4	100.00
ALWAYS	212	55	51	92.73
CONT_ASSIGN	326	1	1	100.00
ALWAYS	329	3	3	100.00
ALWAYS	337	3	3	100.00
ALWAYS	346	7	7	100.00
CONT_ASSIGN	360	1	1	100.00
ALWAYS	363	5	5	100.00
ALWAYS	373	9	9	100.00
ALWAYS	390	3	3	100.00
ALWAYS	402	6	6	100.00
CONT_ASSIGN	418	1	1	100.00
ALWAYS	421	6	6	100.00
CONT_ASSIGN	435	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
90	1	1
131	1	1
132	1	1
134	1	1
140	1	1
144	1	1
148	1	1
152	1	1
157	1	1
163	1	1
164	1	1
171	1	1
172	1	1
175	1	1
176	1	1
178	1	1
184	1	1
185	1	1
187	1	1
188	1	1
189	1	1
190	1	1
			MISSING_ELSE
196	1	1
197	1	1
199	1	1
200	1	1
			MISSING_ELSE
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
221	1	1
225	1	1
226	1	1
227	1	1
229	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	0	1
244	1	1
249	1	1
253	1	1
254	1	1
257	1	1
258	1	1
259	1	1
260	1	1
261	1	1
263	1	1
264	1	1
265	1	1
266	1	1
268	1	1
273	1	1
274	1	1
276	1	1
278	1	1
280	0	1
281	0	1
283	1	1
284	1	1
285	1	1
289	1	1
290	1	1
291	1	1
292	1	1
293	1	1
294	1	1
296	1	1
297	1	1
298	1	1
305	1	1
307	1	1
309	0	1
312	1	1
313	1	1
326	1	1
329	1	1
330	1	1
332	1	1
337	1	1
338	1	1
340	1	1
346	1	1
348	1	1
349	1	1
350	1	1
351	1	1
			MISSING_ELSE
354	1	1
355	1	1
			MISSING_ELSE
360	1	1
363	1	1
364	1	1
365	1	1
366	1	1
368	1	1
373	1	1
374	1	1
375	1	1
376	1	1
378	1	1
379	1	1
380	1	1
381	1	1
383	1	1
390	1	1
391	1	1
393	1	1
402	1	1
403	1	1
405	1	1
406	1	1
407	1	1
408	1	1
			MISSING_ELSE
418	1	1
421	1	1
422	1	1
424	1	1
425	1	1
426	1	1
427	1	1
			MISSING_ELSE
435	1	1

---

Cond Coverage for Module : usb_fs_nb_out_pe

	Total	Covered	Percent
Conditions	134	121	90.30
Logical	134	121	90.30
Non-Logical	0	0
Event	0	0

 LINE       134
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T27,T28
1	0	1	1	Covered	T70,T73,T61
1	1	0	1	Covered	T2,T27,T28
1	1	1	0	Covered	T3,T30,T19
1	1	1	1	Covered	T2,T27,T28

 LINE       134
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       134
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (token_received && (rx_pid == UsbPidOut))
             -------1------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T27
1	0	Covered	T2,T27,T4
1	1	Covered	T2,T27,T28

 LINE       140
 SUB-EXPRESSION (rx_pid == UsbPidOut)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T27

 LINE       144
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T27,T28
1	1	Covered	T2,T4,T5

 LINE       144
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       148
 EXPRESSION (rx_pkt_end_i && ((!rx_pkt_valid_i)))
             ------1-----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T32,T16

 LINE       152
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)))
             ------1-----    -------2------    --------------------------3-------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T27
1	0	1	Covered	T32,T73,T61
1	1	0	Covered	T2,T3,T27
1	1	1	Covered	T1,T2,T27

 LINE       152
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T27

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T27

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       157
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) ))
             ------1-----    -------2------    -----------------------------3----------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T27
1	0	1	Covered	T1,T16,T88
1	1	0	Covered	T1,T2,T27
1	1	1	Covered	T2,T3,T27

 LINE       157
 SUB-EXPRESSION ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) )
                    --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       157
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T27

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T27

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       164
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---

-1-	Status	Tests
0	Covered	T3,T30,T19
1	Covered	T1,T2,T3

 LINE       175
 EXPRESSION (out_ep_enabled_i[out_ep_index_d] & ep_in_hw)
             ----------------1---------------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T30,T83,T73
1	1	Covered	T2,T27,T28

 LINE       178
 EXPRESSION (data_packet_received && ep_active && (rx_pid_i[3] != data_toggle_q[out_ep_index_d]))
             ----------1---------    ----2----    -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T27,T28
1	0	1	Covered	T30,T83,T91
1	1	0	Covered	T2,T27,T28
1	1	1	Covered	T30,T83,T73

 LINE       178
 SUB-EXPRESSION (rx_pid_i[3] != data_toggle_q[out_ep_index_d])
                -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       187
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T28
1	0	Covered	T30,T83,T85
1	1	Covered	T2,T4,T5

 LINE       189
 EXPRESSION (out_token_received && ep_active)
             ---------1--------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T28
1	0	Covered	T30,T83,T73
1	1	Covered	T2,T27,T28

 LINE       225
 EXPRESSION (ep_active && (out_token_received || (setup_token_received && ep_is_control)))
             ----1----    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T83,T73
1	0	Covered	T2,T27,T28
1	1	Covered	T2,T27,T28

 LINE       225
 SUB-EXPRESSION (out_token_received || (setup_token_received && ep_is_control))
                 ---------1--------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T27,T28

 LINE       225
 SUB-EXPRESSION (setup_token_received && ep_is_control)
                 ----------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T30,T83,T45
1	1	Covered	T2,T4,T5

 LINE       241
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------

-1-	Status	Tests
0	Covered	T2,T27,T28
1	Not Covered

 LINE       249
 EXPRESSION (((!ep_is_control)) && out_ep_iso_i[out_ep_index] && data_packet_received)
             ---------1--------    -------------2------------    ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T27,T28,T29
1	1	0	Covered	T92,T93,T94
1	1	1	Covered	T92,T93,T94

 LINE       254
 EXPRESSION (bad_data_toggle && ((!out_ep_stall_i[out_ep_index])))
             -------1-------    ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T28
1	0	Not Covered
1	1	Covered	T67,T68,T69

 LINE       261
 EXPRESSION (invalid_packet_received || non_data_packet_received)
             -----------1-----------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Covered	T61,T95,T96
1	0	Covered	T32,T73,T61

 LINE       278
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Not Covered
1	0	Not Covered

 LINE       292
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Not Covered
1	0	Not Covered

 LINE       307
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------

-1-	-2-	Status	Tests
0	0	Covered	T92,T93,T94
0	1	Not Covered
1	0	Not Covered

 LINE       340
 EXPRESSION (link_reset_i ? StIdle : out_xact_state_next)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       348
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T27,T28
1	0	Covered	T30,T83,T85
1	1	Covered	T2,T4,T5

 LINE       393
 EXPRESSION ((out_xact_state == StRcvdDataStart) && rx_data_put_i)
             -----------------1-----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T30,T83
1	0	Covered	T2,T27,T28
1	1	Covered	T2,T27,T28

 LINE       393
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T27,T28

 LINE       405
 EXPRESSION ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))
             -------------1------------    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T27,T28
0	1	Covered	T2,T27,T28
1	0	Covered	T1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StIdle)
                -------------1------------

-1-	Status	Tests
0	Covered	T2,T27,T28
1	Covered	T1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StRcvdOut)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T27,T28

 LINE       407
 EXPRESSION (out_ep_data_put_o && out_ep_full_i[out_ep_index])
             --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T30,T83,T85
1	0	Covered	T2,T27,T28
1	1	Covered	T30,T83,T85

 LINE       418
 EXPRESSION (((!nak_out_transaction)) && ((~&out_ep_put_addr_o)) && out_ep_data_put_o)
             ------------1-----------    -----------2-----------    --------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T30,T83,T85
1	0	1	Covered	T2,T28,T4
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T2,T27,T28

 LINE       424
 EXPRESSION (out_xact_state == StRcvdOut)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T27,T28

 LINE       426
 EXPRESSION ((out_xact_state == StRcvdDataStart) && increment_addr)
             -----------------1-----------------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T27,T28
1	1	Covered	T2,T27,T28

 LINE       426
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T27,T28

 LINE       435
 EXPRESSION ((out_xact_state == StRcvdDataStart) && (ep_is_control || ((!out_ep_iso_i[out_ep_index]))) && ((!out_ep_stall_i[out_ep_index])) && bad_data_toggle)
             -----------------1-----------------    -------------------------2------------------------    ----------------3----------------    -------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T30,T83,T73
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Covered	T2,T27,T28
1	1	1	1	Covered	T67,T68,T69

 LINE       435
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T27,T28

 LINE       435
 SUB-EXPRESSION (ep_is_control || ((!out_ep_iso_i[out_ep_index])))
                 ------1------    ---------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T92,T93,T94
0	1	Covered	T1,T2,T3
1	0	Not Covered

---

FSM Coverage for Module : usb_fs_nb_out_pe

Summary for FSM :: out_xact_state

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	8	7	87.50
Sequences	0	0

State, Transition and Sequence Details for FSM :: out_xact_state

---

states	Line No.	Covered	Tests
StIdle	340	Covered	T1,T2,T3
StRcvdDataEnd	266	Covered	T2,T27,T28
StRcvdDataStart	240	Covered	T2,T27,T28
StRcvdIsoDataEnd	253	Covered	T92,T93,T94
StRcvdOut	226	Covered	T2,T27,T28

transitions	Line No.	Covered	Tests
StIdle->StRcvdOut	226	Covered	T2,T27,T28
StRcvdDataEnd->StIdle	340	Covered	T2,T27,T28
StRcvdDataStart->StIdle	340	Covered	T32,T73,T61
StRcvdDataStart->StRcvdDataEnd	266	Covered	T2,T27,T28
StRcvdDataStart->StRcvdIsoDataEnd	253	Covered	T92,T93,T94
StRcvdIsoDataEnd->StIdle	340	Covered	T92,T93,T94
StRcvdOut->StIdle	340	Not Covered
StRcvdOut->StRcvdDataStart	240	Covered	T2,T27,T28

---

Branch Coverage for Module : usb_fs_nb_out_pe

	Line No.	Total	Covered	Percent
Branches		53	49	92.45
TERNARY	164	2	2	100.00
IF	184	4	4	100.00
IF	196	3	3	100.00
CASE	221	18	14	77.78
IF	329	2	2	100.00
IF	337	3	3	100.00
IF	348	3	3	100.00
IF	354	2	2	100.00
IF	363	3	3	100.00
IF	373	3	3	100.00
IF	390	2	2	100.00
IF	402	4	4	100.00
IF	421	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	164	(ep_in_hw) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T30,T19

	LineNo.	Expression
-1-:	184	if ((!rst_ni))
-2-:	187	if ((setup_token_received && ep_active))
-3-:	189	if ((out_token_received && ep_active))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Covered	T2,T27,T28
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	196	if ((!rst_ni))
-2-:	199	if (rx_data_put_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T27
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	221	case (out_xact_state)
-2-:	225	if ((ep_active && (out_token_received || (setup_token_received && ep_is_control))))
-3-:	239	if (rx_pkt_start_i)
-4-:	241	if ((timeout_cntdown_q == '0))
-5-:	249	if ((((!ep_is_control) && out_ep_iso_i[out_ep_index]) && data_packet_received))
-6-:	254	if ((bad_data_toggle && (!out_ep_stall_i[out_ep_index])))
-7-:	261	if ((invalid_packet_received || non_data_packet_received))
-8-:	265	if (data_packet_received)
-9-:	276	if (current_xact_setup_q)
-10-:	278	if ((nak_out_transaction | out_ep_full_i[out_ep_index]))
-11-:	289	if (out_ep_stall_i[out_ep_index])
-12-:	292	if ((nak_out_transaction | out_ep_full_i[out_ep_index]))
-13-:	307	if ((nak_out_transaction | out_ep_full_i[out_ep_index]))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T27,T28
StIdle	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StRcvdOut	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T27,T28
StRcvdOut	-	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StRcvdOut	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T2,T27,T28
StRcvdDataStart	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T92,T93,T94
StRcvdDataStart	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T67,T68,T69
StRcvdDataStart	-	-	-	0	0	1	-	-	-	-	-	-	Covered	T32,T73,T61
StRcvdDataStart	-	-	-	0	0	0	1	-	-	-	-	-	Covered	T2,T27,T28
StRcvdDataStart	-	-	-	0	0	0	0	-	-	-	-	-	Covered	T2,T27,T28
StRcvdDataEnd	-	-	-	-	-	-	-	1	1	-	-	-	Not Covered
StRcvdDataEnd	-	-	-	-	-	-	-	1	0	-	-	-	Covered	T2,T4,T5
StRcvdDataEnd	-	-	-	-	-	-	-	0	-	1	-	-	Covered	T29,T30,T20
StRcvdDataEnd	-	-	-	-	-	-	-	0	-	0	1	-	Covered	T30,T83,T85
StRcvdDataEnd	-	-	-	-	-	-	-	0	-	0	0	-	Covered	T2,T27,T28
StRcvdIsoDataEnd	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StRcvdIsoDataEnd	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T92,T93,T94
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	329	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	337	if ((!rst_ni))
-2-:	340	(link_reset_i) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	348	if ((setup_token_received && ep_active))
-2-:	350	if (new_pkt_end)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T5
0	1	Covered	T2,T27,T28
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	354	if (out_datatog_we_i)

Branches:

-1-	Status	Tests
1	Covered	T97,T57,T58
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	363	if ((!rst_ni))
-2-:	365	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	373	if ((!rst_ni))
-2-:	378	if (out_xact_start)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T27,T28
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	390	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	402	if ((!rst_ni))
-2-:	405	if (((out_xact_state == StIdle) || (out_xact_state == StRcvdOut)))
-3-:	407	if ((out_ep_data_put_o && out_ep_full_i[out_ep_index]))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T30,T83,T85
0	0	0	Covered	T2,T27,T28

	LineNo.	Expression
-1-:	421	if ((!rst_ni))
-2-:	424	if ((out_xact_state == StRcvdOut))
-3-:	426	if (((out_xact_state == StRcvdDataStart) && increment_addr))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T27,T28
0	0	1	Covered	T2,T27,T28
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usb_fs_nb_out_pe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutXactStateValid_A	507496517	507289217	0	0

OutXactStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507496517	507289217	0	0
T1	6902	6835	0	0
T2	259625	259553	0	0
T3	10444	10392	0	0
T4	210740	210654	0	0
T5	188523	188433	0	0
T27	161153	161097	0	0
T28	9424	9334	0	0
T29	7247	7165	0	0
T30	561157	561065	0	0
T32	9421	9358	0	0