Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16112217	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16916400	1		T1	22		T2	37		T3	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32386737	1		T1	12		T2	23		T3	2
values[0x0]	320407	1		T1	15		T2	14		T3	2
values[0x1]	321473	1		T1	11		T2	13		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12848803	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20179814	1		T1	28		T2	42		T3	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	95985	1		T7	3		T5	915		T134	1
valid_sources[0x01]	96077	1		T7	4		T5	862		T82	1
valid_sources[0x02]	97896	1		T7	3		T5	856		T8	4
valid_sources[0x03]	96423	1		T1	1		T27	1		T7	3
valid_sources[0x04]	96568	1		T1	1		T5	927		T134	5
valid_sources[0x05]	399739	1		T27	3		T5	1017		T134	1
valid_sources[0x06]	207636	1		T26	13		T18	1		T5	993
valid_sources[0x07]	97001	1		T5	959		T82	2		T136	18
valid_sources[0x08]	95916	1		T27	8		T5	938		T82	13
valid_sources[0x09]	98342	1		T28	1		T5	836		T82	1
valid_sources[0x0a]	267143	1		T1	1		T58	2		T7	2
valid_sources[0x0b]	95949	1		T5	879		T136	37		T39	86
valid_sources[0x0c]	97551	1		T27	1		T5	917		T136	34
valid_sources[0x0d]	122247	1		T7	3		T5	945		T298	1
valid_sources[0x0e]	228385	1		T5	968		T136	25		T39	80
valid_sources[0x0f]	95085	1		T58	1		T5	948		T136	22
valid_sources[0x10]	252501	1		T5	957		T136	19		T39	66
valid_sources[0x11]	252780	1		T27	1		T7	2		T5	960
valid_sources[0x12]	99083	1		T5	1030		T82	1		T136	24
valid_sources[0x13]	97065	1		T28	1		T5	901		T20	1
valid_sources[0x14]	94699	1		T5	1010		T76	1		T136	24
valid_sources[0x15]	97311	1		T7	3		T5	995		T136	32
valid_sources[0x16]	95394	1		T27	6		T7	1		T5	955
valid_sources[0x17]	212205	1		T5	971		T298	1		T136	25
valid_sources[0x18]	221828	1		T5	971		T136	12		T39	80
valid_sources[0x19]	311910	1		T27	2		T29	3		T5	929
valid_sources[0x1a]	96311	1		T7	3		T5	920		T298	1
valid_sources[0x1b]	177954	1		T5	964		T82	3		T136	17
valid_sources[0x1c]	96416	1		T7	5		T5	977		T136	17
valid_sources[0x1d]	96241	1		T5	900		T134	2		T136	15
valid_sources[0x1e]	96070	1		T1	1		T5	968		T136	11
valid_sources[0x1f]	96754	1		T7	7		T5	940		T134	2
valid_sources[0x20]	95389	1		T5	954		T82	3		T134	1
valid_sources[0x21]	96970	1		T5	945		T139	1		T136	17
valid_sources[0x22]	96514	1		T5	977		T136	31		T39	70
valid_sources[0x23]	214838	1		T1	1		T3	2		T28	1
valid_sources[0x24]	97824	1		T5	985		T136	20		T39	76
valid_sources[0x25]	117676	1		T5	992		T134	5		T136	27
valid_sources[0x26]	98960	1		T3	1		T5	930		T136	18
valid_sources[0x27]	95895	1		T1	1		T5	989		T76	1
valid_sources[0x28]	223565	1		T7	2		T5	906		T223	3
valid_sources[0x29]	96146	1		T7	1		T5	948		T136	17
valid_sources[0x2a]	96082	1		T5	888		T134	9		T136	19
valid_sources[0x2b]	95615	1		T5	955		T76	1		T82	5
valid_sources[0x2c]	103825	1		T5	935		T136	28		T39	89
valid_sources[0x2d]	361994	1		T5	987		T8	2		T136	16
valid_sources[0x2e]	95947	1		T31	10		T5	971		T136	37
valid_sources[0x2f]	97045	1		T5	1030		T136	6		T39	78
valid_sources[0x30]	99190	1		T27	2		T5	893		T76	1
valid_sources[0x31]	144908	1		T18	3		T5	969		T76	1
valid_sources[0x32]	94718	1		T27	3		T5	970		T136	24
valid_sources[0x33]	96277	1		T7	1		T5	943		T223	1
valid_sources[0x34]	115592	1		T27	4		T28	1		T5	937
valid_sources[0x35]	97363	1		T5	967		T134	2		T136	24
valid_sources[0x36]	95776	1		T5	934		T298	1		T136	28
valid_sources[0x37]	96428	1		T28	1		T5	907		T76	1
valid_sources[0x38]	99592	1		T1	1		T5	931		T136	23
valid_sources[0x39]	137069	1		T5	916		T94	14		T134	2
valid_sources[0x3a]	97774	1		T1	1		T5	1038		T82	1
valid_sources[0x3b]	163732	1		T1	1		T5	918		T136	6
valid_sources[0x3c]	101684	1		T5	936		T20	1		T134	2
valid_sources[0x3d]	161217	1		T1	1		T5	938		T136	21
valid_sources[0x3e]	96322	1		T28	1		T5	931		T76	1
valid_sources[0x3f]	95729	1		T5	941		T76	2		T82	16
valid_sources[0x40]	96469	1		T28	2		T7	2		T5	949
valid_sources[0x41]	95719	1		T5	954		T19	25		T76	1
valid_sources[0x42]	97898	1		T5	958		T134	16		T136	10
valid_sources[0x43]	103439	1		T5	966		T75	3		T136	23
valid_sources[0x44]	95625	1		T7	1		T5	897		T136	18
valid_sources[0x45]	97767	1		T35	1		T5	963		T136	16
valid_sources[0x46]	162613	1		T1	1		T5	948		T139	2
valid_sources[0x47]	95740	1		T5	970		T8	3		T76	1
valid_sources[0x48]	97713	1		T5	912		T298	2		T82	1
valid_sources[0x49]	96565	1		T1	1		T7	6		T5	813
valid_sources[0x4a]	99456	1		T27	7		T5	910		T76	1
valid_sources[0x4b]	331624	1		T5	995		T134	3		T136	16
valid_sources[0x4c]	95515	1		T7	4		T5	901		T82	8
valid_sources[0x4d]	138072	1		T5	926		T298	1		T82	1
valid_sources[0x4e]	168189	1		T1	1		T5	944		T136	17
valid_sources[0x4f]	213017	1		T27	3		T5	986		T136	18
valid_sources[0x50]	95547	1		T58	1		T5	857		T134	3
valid_sources[0x51]	96177	1		T28	1		T5	931		T20	1
valid_sources[0x52]	96793	1		T5	1041		T82	2		T136	48
valid_sources[0x53]	118970	1		T7	1		T5	964		T136	17
valid_sources[0x54]	96411	1		T5	931		T82	2		T136	18
valid_sources[0x55]	97203	1		T28	2		T7	1		T5	941
valid_sources[0x56]	113642	1		T5	1006		T82	4		T299	1
valid_sources[0x57]	96031	1		T1	1		T5	897		T82	1
valid_sources[0x58]	96443	1		T28	1		T7	1		T5	936
valid_sources[0x59]	96935	1		T5	1033		T134	2		T278	14
valid_sources[0x5a]	218388	1		T7	4		T5	935		T82	10
valid_sources[0x5b]	395675	1		T30	20610		T5	966		T134	1
valid_sources[0x5c]	98362	1		T5	957		T8	4		T76	2
valid_sources[0x5d]	97270	1		T1	1		T5	933		T20	1
valid_sources[0x5e]	99035	1		T5	940		T8	7		T136	23
valid_sources[0x5f]	95386	1		T5	966		T134	1		T136	15
valid_sources[0x60]	97405	1		T5	887		T8	5		T134	2
valid_sources[0x61]	97340	1		T5	986		T136	18		T39	76
valid_sources[0x62]	99075	1		T1	1		T27	5		T7	3
valid_sources[0x63]	119039	1		T3	1		T5	960		T136	13
valid_sources[0x64]	97318	1		T1	1		T7	1		T5	894
valid_sources[0x65]	95580	1		T27	4		T5	976		T136	9
valid_sources[0x66]	109100	1		T1	1		T28	2		T7	1
valid_sources[0x67]	97248	1		T1	2		T58	1		T7	9
valid_sources[0x68]	98332	1		T27	2		T28	1		T5	857
valid_sources[0x69]	97044	1		T5	940		T136	29		T39	100
valid_sources[0x6a]	98571	1		T7	2		T5	968		T136	18
valid_sources[0x6b]	97100	1		T1	1		T5	927		T82	5
valid_sources[0x6c]	96127	1		T5	940		T139	1		T136	25
valid_sources[0x6d]	95983	1		T5	942		T21	8		T82	1
valid_sources[0x6e]	96163	1		T7	4		T5	884		T136	14
valid_sources[0x6f]	96094	1		T5	889		T82	5		T136	22
valid_sources[0x70]	345634	1		T5	1003		T20	2		T136	28
valid_sources[0x71]	97923	1		T5	957		T136	22		T39	74
valid_sources[0x72]	97721	1		T5	974		T20	1		T82	1
valid_sources[0x73]	148755	1		T5	939		T136	18		T39	82
valid_sources[0x74]	237609	1		T1	1		T5	1041		T20	1
valid_sources[0x75]	97570	1		T7	2		T5	939		T298	1
valid_sources[0x76]	165702	1		T5	881		T136	17		T39	69
valid_sources[0x77]	138074	1		T5	951		T76	1		T136	11
valid_sources[0x78]	95942	1		T5	935		T136	29		T39	76
valid_sources[0x79]	96552	1		T7	3		T5	975		T136	30
valid_sources[0x7a]	116766	1		T5	982		T82	2		T136	8
valid_sources[0x7b]	340497	1		T5	948		T298	1		T136	27
valid_sources[0x7c]	96385	1		T27	1		T58	1		T5	958
valid_sources[0x7d]	336897	1		T1	1		T7	1		T5	965
valid_sources[0x7e]	95810	1		T5	916		T134	7		T136	14
valid_sources[0x7f]	97044	1		T5	947		T136	24		T39	82
valid_sources[0x80]	96456	1		T7	1		T5	988		T82	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16402302

1

T1

6

T2

19

T33

2

values[0x0]

all_enables

biggest_size

264829

1

T1

10

T2

12

T33

3

values[0x1]

all_enables

biggest_size

249269

1

T1

6

T2

6

T3

3