Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	16127248	1		T1	16		T2	13		T3	7
full_word	16917534	1		T1	22		T2	37		T3	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33044472	1		T1	38		T2	50		T3	10
auto[TlIntgErrCmd]	98	1		T196	7		T216	4		T220	3
auto[TlIntgErrData]	105	1		T196	5		T216	11		T220	3
auto[TlIntgErrBoth]	107	1		T196	8		T216	5		T220	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32388752	1		T1	12		T2	23		T3	2
auto[1]	656030	1		T1	26		T2	27		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15986119	1		T1	6		T2	4		T3	2
auto[TlIntgErrNone]	partial	auto[1]	140846	1		T1	10		T2	9		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	16402494	1		T1	6		T2	19		T33	2
auto[TlIntgErrNone]	full_word	auto[1]	515013	1		T1	16		T2	18		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T196	1		T216	2		T220	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T196	6		T216	2		T220	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T292	1		T289	1		T293	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T288	1		T294	1		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1		T216	6		T220	3		T235	1
auto[TlIntgErrData]	partial	auto[1]	50	1		T196	4		T216	3		T235	3
auto[TlIntgErrData]	full_word	auto[0]	7	1		T196	1		T216	1		T235	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T216	1		T295	1		T291	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T196	5		T216	3		T235	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T196	2		T216	2		T220	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T196	1		T289	2		T296	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T220	1		T297	1		-	-