Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	505505715	12776	0	0
ep_in_enable_rd_A	505505715	4168	0	0
ep_out_enable_rd_A	505505715	3635	0	0
in_iso_rd_A	505505715	3948	0	0
intr_enable_rd_A	505505715	5883	0	0
out_iso_rd_A	505505715	3835	0	0
phy_config_rd_A	505505715	2189	0	0
phy_pins_drive_rd_A	505505715	3020	0	0
rxenable_setup_rd_A	505505715	3582	0	0
set_nak_out_rd_A	505505715	3569	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505505715	12776	0	0
T196	40893	3	0	0
T197	8153	13	0	0
T198	9969	745	0	0
T215	11209	661	0	0
T216	104543	5	0	0
T220	21512	2	0	0
T221	8061	9	0	0
T224	15337	847	0	0
T225	5063	683	0	0
T231	5649	12	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505505715	4168	0	0
T196	40893	434	0	0
T216	104543	518	0	0
T220	21512	191	0	0
T221	8061	29	0	0
T233	7807	45	0	0
T235	21644	297	0	0
T248	2940	6	0	0
T250	17875	179	0	0
T252	3687	9	0	0
T264	9432	14	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505505715	3635	0	0
T196	40893	398	0	0
T216	104543	406	0	0
T220	21512	104	0	0
T221	8061	2	0	0
T233	7807	15	0	0
T235	21644	305	0	0
T248	2940	6	0	0
T250	17875	205	0	0
T252	3687	5	0	0
T264	9432	4	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505505715	3948	0	0
T196	40893	380	0	0
T216	104543	545	0	0
T220	21512	210	0	0
T221	8061	49	0	0
T233	7807	40	0	0
T235	21644	295	0	0
T248	2940	33	0	0
T250	17875	184	0	0
T252	3687	6	0	0
T264	9432	23	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505505715	5883	0	0
T196	40893	987	0	0
T203	1969	19	0	0
T204	3017	14	0	0
T216	104543	671	0	0
T220	21512	287	0	0
T221	8061	80	0	0
T248	2940	91	0	0
T250	17875	175	0	0
T252	3687	165	0	0
T264	9432	29	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505505715	3835	0	0
T196	40893	527	0	0
T216	104543	525	0	0
T220	21512	130	0	0
T221	8061	54	0	0
T233	7807	11	0	0
T235	21644	261	0	0
T248	2940	6	0	0
T250	17875	197	0	0
T252	3687	2	0	0
T264	9432	31	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505505715	2189	0	0
T196	40893	252	0	0
T216	104543	223	0	0
T220	21512	49	0	0
T221	8061	9	0	0
T233	7807	14	0	0
T235	21644	115	0	0
T248	2940	1	0	0
T250	17875	192	0	0
T252	3687	20	0	0
T264	9432	26	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505505715	3020	0	0
T196	40893	396	0	0
T216	104543	252	0	0
T220	21512	91	0	0
T221	8061	5	0	0
T224	15337	5	0	0
T235	21644	243	0	0
T248	2940	37	0	0
T250	17875	168	0	0
T252	3687	18	0	0
T264	9432	18	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505505715	3582	0	0
T196	40893	460	0	0
T216	104543	463	0	0
T220	21512	180	0	0
T221	8061	48	0	0
T224	15337	4	0	0
T233	7807	36	0	0
T235	21644	231	0	0
T248	2940	44	0	0
T250	17875	179	0	0
T252	3687	54	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505505715	3569	0	0
T196	40893	407	0	0
T216	104543	257	0	0
T220	21512	193	0	0
T221	8061	41	0	0
T233	7807	4	0	0
T235	21644	312	0	0
T248	2940	39	0	0
T250	17875	198	0	0
T252	3687	50	0	0
T264	9432	19	0	0