Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usbdev_usbif
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.01 98.89 97.59 95.56 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl 98.01 98.89 97.59 95.56 100.00



Module Instance : tb.dut.usbdev_impl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.01 98.89 97.59 95.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.10 97.96 95.24 73.44 93.86 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.03 97.53 88.06 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_usb_fs_nb_pe 93.29 98.94 95.44 75.68 96.40 100.00
u_usbdev_linkstate 87.34 92.19 91.76 70.37 82.35 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usbdev_usbif
Line No.TotalCoveredPercent
TOTAL908998.89
CONT_ASSIGN13411100.00
CONT_ASSIGN15200
CONT_ASSIGN15311100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN15711100.00
ALWAYS16066100.00
CONT_ASSIGN18211100.00
ALWAYS18666100.00
ALWAYS1981111100.00
CONT_ASSIGN21811100.00
CONT_ASSIGN21911100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22711100.00
CONT_ASSIGN22911100.00
CONT_ASSIGN23011100.00
CONT_ASSIGN23111100.00
CONT_ASSIGN23211100.00
CONT_ASSIGN23411100.00
CONT_ASSIGN23811100.00
CONT_ASSIGN24011100.00
CONT_ASSIGN24611100.00
ALWAYS24955100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26111100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN27900
CONT_ASSIGN28011100.00
CONT_ASSIGN28411100.00
ALWAYS28622100.00
ALWAYS29333100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30111100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN40611100.00
CONT_ASSIGN40711100.00
ALWAYS41055100.00
ALWAYS41933100.00
ALWAYS459161593.75
CONT_ASSIGN47611100.00
CONT_ASSIGN47711100.00
CONT_ASSIGN47811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
134 1 1
152 unreachable
153 1 1
155 1 1
156 1 1
157 1 1
160 1 1
161 1 1
163 1 1
167 1 1
168 1 1
169 unreachable
170 unreachable
172 unreachable
176 1 1
182 1 1
186 1 1
188 1 1
189 1 1
190 1 1
191 1 1
192 1 1
198 1 1
199 1 1
200 1 1
201 1 1
202 1 1
203 1 1
204 1 1
206 1 1
207 1 1
209 1 1
210 1 1
MISSING_ELSE
218 1 1
219 1 1
224 1 1
227 1 1
229 1 1
230 1 1
231 1 1
232 1 1
234 1 1
238 1 1
240 1 1
246 1 1
249 1 1
250 1 1
251 1 1
253 1 1
254 1 1
259 1 1
261 1 1
263 1 1
264 1 1
269 1 1
279 unreachable
280 1 1
284 1 1
286 1 1
287 1 1
293 1 1
294 1 1
296 1 1
300 1 1
301 1 1
303 1 1
406 1 1
407 1 1
410 1 1
411 1 1
412 1 1
413 1 1
414 1 1
MISSING_ELSE
419 1 1
420 1 1
422 1 1
459 1 1
460 1 1
461 1 1
462 1 1
465 2 2
466 1 2
MISSING_ELSE
468 2 2
469 2 2
MISSING_ELSE
471 2 2
472 2 2
MISSING_ELSE
476 1 1
477 1 1
478 1 1


Cond Coverage for Module : usbdev_usbif
TotalCoveredPercent
Conditions838197.59
Logical838197.59
Non-Logical00
Event00

 LINE       134
 EXPRESSION (connect_en_i & usb_sense_i)
             ------1-----   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T33
10CoveredT34,T8,T10
11CoveredT1,T2,T3

 LINE       153
 EXPRESSION (out_endpoint_val_o ? out_ep_current : '0)
             ---------1--------
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       156
 EXPRESSION (((~connect_en_i)) | link_reset)
             --------1--------   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       160
 EXPRESSION (out_ep_acked || out_ep_rollback)
             ------1-----    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T33,T58
10CoveredT1,T2,T26

 LINE       182
 EXPRESSION (out_ep_data_put & (int'(out_max_used_q) < (MaxPktSizeByte - 1)) & (out_ep_put_addr[1:0] == 2'b11))
             -------1-------   ----------------------2----------------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101UnreachableT27,T30,T5
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       182
 SUB-EXPRESSION (out_ep_put_addr[1:0] == 2'b11)
                ---------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       218
 EXPRESSION (current_setup ? avsetup_rvalid_i : avout_rvalid_i)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T28

 LINE       219
 EXPRESSION (current_setup ? avsetup_rdata_i : avout_rdata_i)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T28

 LINE       224
 EXPRESSION (current_setup ? rx_wready_setup_i : rx_wready_out_i)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T28

 LINE       227
 EXPRESSION (av_rvalid & (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)))
             ----1----   ---------------------------------------------2---------------------------------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       227
 SUB-EXPRESSION (std_write_q | (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked))
                 -----1-----   -------------------------------------2-------------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T26
10CoveredT1,T2,T3

 LINE       227
 SUB-EXPRESSION (((~out_max_used_q[PktW])) & (out_max_used_q[1:0] != 2'b11) & out_ep_acked)
                 ------------1------------   ---------------2--------------   ------3-----
-1--2--3-StatusTests
011CoveredT27,T30,T5
101CoveredT2,T27,T5
110CoveredT1,T2,T3
111CoveredT1,T2,T26

 LINE       227
 SUB-EXPRESSION (out_max_used_q[1:0] != 2'b11)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       231
 EXPRESSION (mem_write_o ? mem_waddr : mem_raddr)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       232
 EXPRESSION (mem_read | mem_write_o)
             ----1---   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T26

 LINE       253
 EXPRESSION (rx_wvalid_o & current_setup)
             -----1-----   ------2------
-1--2-StatusTests
01CoveredT1,T2,T28
10CoveredT1,T2,T26
11CoveredT1,T2,T28

 LINE       254
 EXPRESSION (rx_wvalid_o & ((~current_setup)))
             -----1-----   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T28
11CoveredT1,T2,T26

 LINE       261
 EXPRESSION (((~rx_wready)) | ((~av_rvalid)))
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT43,T85,T86

 LINE       269
 EXPRESSION (current_setup & rx_wvalid_o)
             ------1------   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T26
10CoveredT1,T2,T28
11CoveredT1,T2,T28

 LINE       280
 EXPRESSION (in_endpoint_val_o ? in_ep_current : '0)
             --------1--------
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3

 LINE       284
 EXPRESSION ({1'b0, in_ep_get_addr} == in_size_i)
            ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       301
 EXPRESSION (pkt_start_rd | (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0)))
             ------1-----   ------------------------2-----------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T26
10CoveredT1,T2,T26

 LINE       301
 SUB-EXPRESSION (in_ep_data_get & (in_ep_get_addr[1:0] == 2'b0))
                 -------1------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T26
11CoveredT1,T2,T26

 LINE       301
 SUB-EXPRESSION (in_ep_get_addr[1:0] == 2'b0)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (in_ep_get_addr[1] ? (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16]) : (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0]))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T26

 LINE       303
 SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[31:24] : mem_rdata_i[23:16])
                 --------1--------
-1-StatusTests
0CoveredT1,T2,T26
1CoveredT1,T2,T26

 LINE       303
 SUB-EXPRESSION (in_ep_get_addr[0] ? mem_rdata_i[15:8] : mem_rdata_i[7:0])
                 --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T26

 LINE       407
 EXPRESSION (frame_q != frame_d)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T34,T30

 LINE       413
 EXPRESSION (sof_detected_o | do_internal_sof)
             -------1------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T7,T18
10CoveredT212,T213,T214

 LINE       466
 EXPRESSION (out_ep_data_put & current_setup & ((!avsetup_rvalid_i)))
             -------1-------   ------2------   ----------3----------
-1--2--3-StatusTests
011CoveredT1,T2,T28
101CoveredT1,T2,T3
110CoveredT1,T2,T28
111Not Covered

 LINE       469
 EXPRESSION (out_ep_data_put & ((!current_setup)) & ((!avout_rvalid_i)))
             -------1-------   ---------2--------   ---------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T28
110CoveredT1,T2,T3
111CoveredT66,T67,T68

 LINE       472
 EXPRESSION (out_ep_data_put & ((!rx_wready)))
             -------1-------   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT50,T66,T67

Branch Coverage for Module : usbdev_usbif
Line No.TotalCoveredPercent
Branches 45 43 95.56
TERNARY 153 1 1 100.00
TERNARY 218 2 2 100.00
TERNARY 219 2 2 100.00
TERNARY 224 2 2 100.00
TERNARY 231 2 2 100.00
TERNARY 280 1 1 100.00
TERNARY 303 4 4 100.00
IF 160 3 3 100.00
CASE 188 5 4 80.00
IF 198 4 4 100.00
IF 249 2 2 100.00
IF 293 2 2 100.00
IF 411 3 3 100.00
IF 419 2 2 100.00
IF 459 10 9 90.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_usbif.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 153 (out_endpoint_val_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 218 (current_setup) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 219 (current_setup) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 224 (current_setup) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 231 (mem_write_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 280 (in_endpoint_val_o) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable


LineNo. Expression -1-: 303 (in_ep_get_addr[1]) ? -2-: 303 (in_ep_get_addr[0]) ? -3-: 303 (in_ep_get_addr[0]) ?

Branches:
-1--2--3-StatusTests
1 1 - Covered T1,T2,T26
1 0 - Covered T1,T2,T26
0 - 1 Covered T1,T2,T26
0 - 0 Covered T1,T2,T3


LineNo. Expression -1-: 160 if ((out_ep_acked || out_ep_rollback)) -2-: 163 if (out_ep_data_put) -3-: 167 if ((int'(out_max_used_q) < (MaxPktSizeByte - 1))) -4-: 169 if ((int'(out_max_used_q) < (MaxPktSizeByte + 1)))

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 1 - Covered T1,T2,T3
0 1 0 1 Unreachable T27,T30,T5
0 1 0 0 Unreachable
0 0 - - Covered T1,T2,T3


LineNo. Expression -1-: 188 case (out_ep_put_addr[1:0])

Branches:
-1-StatusTests
0 Covered T1,T2,T3
1 Covered T1,T2,T3
2 Covered T1,T2,T3
3 Covered T1,T2,T3
default Not Covered


LineNo. Expression -1-: 198 if ((!rst_ni)) -2-: 202 if (link_reset) -3-: 209 if (out_ep_data_put)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 249 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 293 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 411 if (sof_valid) -2-: 413 if ((sof_detected_o | do_internal_sof))

Branches:
-1--2-StatusTests
1 - Covered T34,T30,T39
0 1 Covered T4,T7,T18
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 419 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 459 if ((!rst_ni)) -2-: 465 if (out_ep_newpkt) -3-: 466 if (((out_ep_data_put & current_setup) & (!avsetup_rvalid_i))) -4-: 468 if (out_ep_newpkt) -5-: 469 if (((out_ep_data_put & (!current_setup)) & (!avout_rvalid_i))) -6-: 471 if (out_ep_newpkt) -7-: 472 if ((out_ep_data_put & (!rx_wready)))

Branches:
-1--2--3--4--5--6--7-StatusTests
1 - - - - - - Covered T1,T2,T3
0 1 - - - - - Covered T1,T2,T3
0 0 1 - - - - Not Covered
0 0 0 - - - - Covered T1,T2,T3
0 - - 1 - - - Covered T1,T2,T3
0 - - 0 1 - - Covered T66,T67,T68
0 - - 0 0 - - Covered T1,T2,T3
0 - - - - 1 - Covered T1,T2,T3
0 - - - - 0 1 Covered T50,T66,T67
0 - - - - 0 0 Covered T1,T2,T3


Assert Coverage for Module : usbdev_usbif
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ParamAVFifoWidthValid 2676 2676 0 0
ParamMaxPktSizeByteValid 2676 2676 0 0
ParamNBufValid 2676 2676 0 0
ParamNEndpointsValid 2676 2676 0 0
ParamRXFifoWidthValid 2676 2676 0 0
ParamSramAwValid 2676 2676 0 0


ParamAVFifoWidthValid
NameAttemptsReal SuccessesFailuresIncomplete
Total 2676 2676 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T35 1 1 0 0

ParamMaxPktSizeByteValid
NameAttemptsReal SuccessesFailuresIncomplete
Total 2676 2676 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T35 1 1 0 0

ParamNBufValid
NameAttemptsReal SuccessesFailuresIncomplete
Total 2676 2676 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T35 1 1 0 0

ParamNEndpointsValid
NameAttemptsReal SuccessesFailuresIncomplete
Total 2676 2676 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T35 1 1 0 0

ParamRXFifoWidthValid
NameAttemptsReal SuccessesFailuresIncomplete
Total 2676 2676 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T35 1 1 0 0

ParamSramAwValid
NameAttemptsReal SuccessesFailuresIncomplete
Total 2676 2676 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T26 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T35 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%