Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14522275	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	15310695	1		T1	15117		T2	5		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29205701	1		T1	29852		T2	2		T3	5
values[0x0]	313442	1		T1	129		T2	4		T3	3
values[0x1]	313827	1		T1	143		T2	3		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11574161	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	18258809	1		T1	18080		T2	7		T3	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	87269	1		T1	233		T4	345		T30	163
valid_sources[0x01]	88644	1		T1	149		T4	392		T30	119
valid_sources[0x02]	214778	1		T1	87		T4	389		T30	138
valid_sources[0x03]	86918	1		T1	133		T4	309		T30	114
valid_sources[0x04]	152027	1		T1	87		T4	446		T30	165
valid_sources[0x05]	111311	1		T1	78		T4	333		T30	135
valid_sources[0x06]	88629	1		T1	78		T4	325		T30	144
valid_sources[0x07]	123117	1		T1	126		T4	382		T30	146
valid_sources[0x08]	89506	1		T1	148		T4	284		T30	169
valid_sources[0x09]	149277	1		T1	160		T4	372		T30	205
valid_sources[0x0a]	88346	1		T1	151		T28	2		T4	359
valid_sources[0x0b]	89415	1		T1	164		T4	281		T30	137
valid_sources[0x0c]	88034	1		T1	155		T4	425		T30	145
valid_sources[0x0d]	362588	1		T1	122		T4	336		T30	164
valid_sources[0x0e]	87708	1		T1	103		T4	331		T30	134
valid_sources[0x0f]	88747	1		T1	123		T4	351		T30	157
valid_sources[0x10]	87978	1		T1	96		T4	395		T30	184
valid_sources[0x11]	302690	1		T1	73		T4	404		T30	187
valid_sources[0x12]	90186	1		T1	246		T4	337		T30	145
valid_sources[0x13]	87828	1		T1	103		T2	3		T4	336
valid_sources[0x14]	87967	1		T1	104		T4	334		T30	130
valid_sources[0x15]	88025	1		T1	21		T4	368		T30	134
valid_sources[0x16]	87717	1		T1	61		T4	453		T30	138
valid_sources[0x17]	93371	1		T1	129		T4	449		T30	169
valid_sources[0x18]	171048	1		T1	159		T4	377		T30	163
valid_sources[0x19]	89742	1		T1	107		T3	1		T4	398
valid_sources[0x1a]	91262	1		T1	161		T28	1		T4	376
valid_sources[0x1b]	88504	1		T1	142		T4	317		T30	141
valid_sources[0x1c]	89459	1		T1	78		T28	1		T4	348
valid_sources[0x1d]	89281	1		T1	116		T4	285		T30	167
valid_sources[0x1e]	116475	1		T1	186		T4	383		T30	188
valid_sources[0x1f]	89741	1		T1	223		T3	1		T4	358
valid_sources[0x20]	86944	1		T1	90		T4	328		T30	149
valid_sources[0x21]	88775	1		T1	42		T4	314		T30	136
valid_sources[0x22]	821131	1		T1	140		T4	407		T30	153
valid_sources[0x23]	88734	1		T1	112		T3	1		T4	391
valid_sources[0x24]	89371	1		T1	137		T4	273		T30	155
valid_sources[0x25]	87179	1		T1	49		T4	375		T30	156
valid_sources[0x26]	87041	1		T1	63		T4	338		T30	144
valid_sources[0x27]	87636	1		T1	87		T4	461		T30	137
valid_sources[0x28]	87938	1		T1	161		T4	396		T30	151
valid_sources[0x29]	87911	1		T1	102		T4	366		T30	183
valid_sources[0x2a]	245367	1		T1	109		T28	1		T4	394
valid_sources[0x2b]	88798	1		T1	134		T4	415		T30	141
valid_sources[0x2c]	134683	1		T1	148		T28	1		T4	422
valid_sources[0x2d]	88448	1		T1	121		T4	409		T30	176
valid_sources[0x2e]	87235	1		T1	105		T28	1		T4	377
valid_sources[0x2f]	89396	1		T1	62		T4	338		T30	139
valid_sources[0x30]	114293	1		T1	114		T28	1		T4	320
valid_sources[0x31]	267251	1		T1	129		T4	356		T30	111
valid_sources[0x32]	148163	1		T1	139		T27	7		T4	375
valid_sources[0x33]	88655	1		T1	66		T3	1		T4	421
valid_sources[0x34]	89474	1		T1	74		T4	338		T30	149
valid_sources[0x35]	265244	1		T1	137		T4	317		T30	162
valid_sources[0x36]	87581	1		T1	97		T4	457		T30	190
valid_sources[0x37]	122488	1		T1	22		T4	418		T30	169
valid_sources[0x38]	87405	1		T1	80		T4	328		T30	164
valid_sources[0x39]	119807	1		T1	84		T4	327		T30	157
valid_sources[0x3a]	116807	1		T1	183		T4	298		T30	133
valid_sources[0x3b]	86240	1		T1	246		T4	328		T30	175
valid_sources[0x3c]	125640	1		T1	99		T4	361		T30	171
valid_sources[0x3d]	87659	1		T1	89		T4	298		T30	145
valid_sources[0x3e]	86669	1		T1	40		T4	290		T30	150
valid_sources[0x3f]	247148	1		T1	170		T4	433		T30	150
valid_sources[0x40]	89206	1		T1	74		T4	306		T30	147
valid_sources[0x41]	88025	1		T1	143		T28	4		T4	371
valid_sources[0x42]	128317	1		T1	77		T4	386		T30	208
valid_sources[0x43]	87713	1		T1	84		T4	393		T30	171
valid_sources[0x44]	118861	1		T1	119		T4	294		T30	152
valid_sources[0x45]	86677	1		T1	170		T28	1		T4	387
valid_sources[0x46]	86121	1		T1	137		T4	427		T30	149
valid_sources[0x47]	255952	1		T1	206		T4	411		T30	157
valid_sources[0x48]	87209	1		T1	42		T4	368		T30	131
valid_sources[0x49]	87255	1		T1	70		T4	440		T30	188
valid_sources[0x4a]	87978	1		T1	74		T4	477		T30	130
valid_sources[0x4b]	88139	1		T1	103		T4	465		T30	147
valid_sources[0x4c]	87756	1		T1	31		T4	321		T30	184
valid_sources[0x4d]	87308	1		T1	79		T4	459		T30	172
valid_sources[0x4e]	88634	1		T1	105		T4	348		T30	160
valid_sources[0x4f]	86363	1		T1	67		T28	1		T4	368
valid_sources[0x50]	292118	1		T1	135		T4	458		T30	141
valid_sources[0x51]	87355	1		T1	57		T4	386		T30	146
valid_sources[0x52]	108790	1		T1	109		T4	367		T30	150
valid_sources[0x53]	87926	1		T1	120		T4	355		T30	154
valid_sources[0x54]	94680	1		T1	78		T4	423		T30	137
valid_sources[0x55]	215717	1		T1	88		T4	376		T30	166
valid_sources[0x56]	202047	1		T1	104		T4	374		T30	136
valid_sources[0x57]	87823	1		T1	98		T4	441		T30	147
valid_sources[0x58]	132423	1		T1	123		T4	356		T30	140
valid_sources[0x59]	88891	1		T1	82		T3	1		T4	311
valid_sources[0x5a]	87553	1		T1	157		T4	278		T30	146
valid_sources[0x5b]	189891	1		T1	122		T28	2		T4	293
valid_sources[0x5c]	88271	1		T1	182		T4	425		T30	166
valid_sources[0x5d]	223694	1		T1	109		T4	403		T30	142
valid_sources[0x5e]	88364	1		T1	179		T4	414		T30	216
valid_sources[0x5f]	88393	1		T1	121		T4	305		T30	138
valid_sources[0x60]	87173	1		T1	126		T4	341		T30	176
valid_sources[0x61]	86837	1		T1	140		T28	1		T4	421
valid_sources[0x62]	86962	1		T1	101		T4	434		T30	116
valid_sources[0x63]	88912	1		T1	29		T4	315		T30	181
valid_sources[0x64]	88887	1		T1	187		T4	393		T30	187
valid_sources[0x65]	88411	1		T1	54		T28	1		T4	448
valid_sources[0x66]	88073	1		T1	112		T4	332		T30	155
valid_sources[0x67]	88080	1		T1	139		T4	314		T30	188
valid_sources[0x68]	87277	1		T1	164		T4	370		T30	182
valid_sources[0x69]	88051	1		T1	78		T4	465		T30	153
valid_sources[0x6a]	122294	1		T1	76		T4	415		T30	133
valid_sources[0x6b]	87921	1		T1	161		T4	429		T30	179
valid_sources[0x6c]	120965	1		T1	142		T4	394		T30	146
valid_sources[0x6d]	108646	1		T1	128		T4	324		T30	147
valid_sources[0x6e]	88615	1		T1	206		T4	432		T30	141
valid_sources[0x6f]	88073	1		T1	176		T4	459		T30	116
valid_sources[0x70]	118375	1		T1	109		T35	11		T4	390
valid_sources[0x71]	88726	1		T1	201		T4	307		T30	131
valid_sources[0x72]	123413	1		T1	78		T4	409		T30	188
valid_sources[0x73]	89340	1		T1	98		T4	360		T30	179
valid_sources[0x74]	115652	1		T1	141		T4	359		T30	152
valid_sources[0x75]	250013	1		T1	99		T4	395		T30	137
valid_sources[0x76]	87809	1		T1	204		T4	354		T30	171
valid_sources[0x77]	87942	1		T1	95		T4	306		T30	151
valid_sources[0x78]	88198	1		T1	151		T28	1		T4	327
valid_sources[0x79]	86965	1		T1	63		T4	375		T30	134
valid_sources[0x7a]	112507	1		T1	159		T4	343		T30	144
valid_sources[0x7b]	111612	1		T1	180		T4	347		T30	159
valid_sources[0x7c]	88065	1		T1	106		T4	403		T30	190
valid_sources[0x7d]	88079	1		T1	65		T4	388		T30	149
valid_sources[0x7e]	89972	1		T1	138		T28	1		T4	345
valid_sources[0x7f]	108803	1		T1	65		T4	371		T30	165
valid_sources[0x80]	87672	1		T1	104		T28	1		T4	388

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14808007

1

T1

14927

T2

2

T3

3

values[0x0]

all_enables

biggest_size

259383

1

T1

91

T2

3

T3

2

values[0x1]

all_enables

biggest_size

243305

1

T1

99

T3

1

T35

2