Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14537722	1		T1	15007		T2	4		T3	6
full_word	15311739	1		T1	15117		T2	5		T3	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	29849181	1		T1	30124		T2	9		T3	12
auto[TlIntgErrCmd]	94	1		T180	8		T181	4		T182	5
auto[TlIntgErrData]	93	1		T180	8		T181	4		T182	3
auto[TlIntgErrBoth]	93	1		T180	4		T181	2		T182	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29207549	1		T1	29852		T2	2		T3	5
auto[1]	641912	1		T1	272		T2	7		T3	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14399261	1		T1	14925		T3	2		T27	4
auto[TlIntgErrNone]	partial	auto[1]	138206	1		T1	82		T2	4		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	14808173	1		T1	14927		T2	2		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	503541	1		T1	190		T2	3		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T180	3		T181	1		T182	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T180	5		T181	3		T182	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T208	1		T276	1		T277	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T231	1		T230	1		T275	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T180	4		T181	2		T182	1
auto[TlIntgErrData]	partial	auto[1]	43	1		T180	2		T181	2		T182	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T180	1		T276	1		T278	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T180	1		T182	1		T273	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T180	2		T182	1		T208	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T180	2		T181	2		T182	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T275	2		T279	1		T277	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T279	1		T280	1		T281	1