Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	507426063	11847	0	0
ep_in_enable_rd_A	507426063	2461	0	0
ep_out_enable_rd_A	507426063	2882	0	0
in_iso_rd_A	507426063	2939	0	0
intr_enable_rd_A	507426063	4571	0	0
out_iso_rd_A	507426063	2782	0	0
phy_config_rd_A	507426063	1862	0	0
phy_pins_drive_rd_A	507426063	2059	0	0
rxenable_setup_rd_A	507426063	2789	0	0
set_nak_out_rd_A	507426063	2921	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507426063	11847	0	0
T180	27826	5	0	0
T181	38503	1	0	0
T182	18067	4	0	0
T208	19989	1	0	0
T209	5476	351	0	0
T210	3247	498	0	0
T211	15579	842	0	0
T221	4433	481	0	0
T223	6043	303	0	0
T230	55545	9	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507426063	2461	0	0
T181	38503	74	0	0
T184	10012	23	0	0
T214	20154	19	0	0
T230	55545	386	0	0
T245	3686	5	0	0
T252	2581	8	0	0
T255	3251	53	0	0
T260	4870	7	0	0
T261	5344	67	0	0
T262	9676	43	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507426063	2882	0	0
T181	38503	138	0	0
T184	10012	42	0	0
T214	20154	21	0	0
T230	55545	464	0	0
T245	3686	10	0	0
T250	8265	46	0	0
T255	3251	25	0	0
T260	4870	13	0	0
T261	5344	60	0	0
T262	9676	59	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507426063	2939	0	0
T181	38503	174	0	0
T184	10012	31	0	0
T214	20154	38	0	0
T230	55545	516	0	0
T245	3686	2	0	0
T252	2581	13	0	0
T255	3251	36	0	0
T260	4870	1	0	0
T261	5344	51	0	0
T262	9676	34	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507426063	4571	0	0
T181	38503	279	0	0
T184	10012	31	0	0
T191	3123	10	0	0
T194	3420	15	0	0
T214	20154	25	0	0
T230	55545	1029	0	0
T252	2581	2	0	0
T255	3251	4	0	0
T260	4870	4	0	0
T263	2949	19	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507426063	2782	0	0
T181	38503	98	0	0
T184	10012	34	0	0
T214	20154	36	0	0
T230	55545	588	0	0
T245	3686	9	0	0
T250	8265	28	0	0
T252	2581	3	0	0
T260	4870	10	0	0
T261	5344	59	0	0
T262	9676	2	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507426063	1862	0	0
T181	38503	98	0	0
T184	10012	48	0	0
T214	20154	37	0	0
T230	55545	260	0	0
T250	8265	37	0	0
T252	2581	11	0	0
T255	3251	5	0	0
T260	4870	14	0	0
T261	5344	20	0	0
T262	9676	20	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507426063	2059	0	0
T181	38503	77	0	0
T184	10012	81	0	0
T214	20154	17	0	0
T230	55545	300	0	0
T245	3686	22	0	0
T252	2581	3	0	0
T255	3251	5	0	0
T260	4870	2	0	0
T261	5344	61	0	0
T262	9676	43	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507426063	2789	0	0
T181	38503	110	0	0
T184	10012	30	0	0
T214	20154	35	0	0
T230	55545	272	0	0
T250	8265	46	0	0
T252	2581	9	0	0
T255	3251	48	0	0
T260	4870	11	0	0
T261	5344	3	0	0
T262	9676	38	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	507426063	2921	0	0
T181	38503	61	0	0
T184	10012	41	0	0
T214	20154	12	0	0
T230	55545	428	0	0
T250	8265	33	0	0
T252	2581	7	0	0
T255	3251	26	0	0
T260	4870	7	0	0
T261	5344	83	0	0
T262	9676	6	0	0