Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	100.00				50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic	68.52	100.00	55.56				50.00
tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic	72.22	100.00	66.67				50.00
tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic	75.93	100.00	77.78				50.00
tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic	79.63	100.00	88.89				50.00
tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic	83.33	100.00	100.00				50.00

---

Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.52	100.00	55.56				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.52	100.00	55.56				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_mux_tx_se0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.22	100.00	66.67				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.22	100.00	66.67				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_mux_tx_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.93	100.00	77.78				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.93	100.00	77.78				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_mux_tx_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.63	100.00	88.89				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.63	100.00	88.89				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_mux_tx_dn

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	100.00				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	100.00				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_mux_tx_dp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T25,T26

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	13395902	13384202	0	0
selKnown1	102	0	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	13395902	13384202	0	0
T1	12092	12087	0	0
T2	22	17	0	0
T3	22	17	0	0
T4	29066	29061	0	0
T5	63308	63303	0	0
T6	0	2	0	0
T16	0	74	0	0
T27	22	17	0	0
T28	283	278	0	0
T29	22	17	0	0
T30	15854	15849	0	0
T31	8	17	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	2	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	102	0	0	0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T25,T26
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	146020	143908	0	0
selKnown1	0	0	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	146020	143908	0	0
T1	133	132	0	0
T2	1	0	0	0
T3	1	0	0	0
T4	252	251	0	0
T5	90	89	0	0
T6	0	1	0	0
T16	0	37	0	0
T27	1	0	0	0
T28	3	2	0	0
T29	1	0	0	0
T30	174	173	0	0
T31	1	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	6	66.67
Logical	9	6	66.67
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T25,T26
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4375187	4372506	0	0
selKnown1	0	0	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4375187	4372506	0	0
T1	3949	3948	0	0
T2	7	6	0	0
T3	7	6	0	0
T4	9537	9536	0	0
T5	21048	21047	0	0
T27	7	6	0	0
T28	92	91	0	0
T29	7	6	0	0
T30	5181	5180	0	0
T31	0	6	0	0
T35	1	0	0	0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T25,T26

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Not Covered
1	1	Covered	T24,T25,T26

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	146021	143908	0	0
selKnown1	50	0	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	146021	143908	0	0
T1	133	132	0	0
T2	1	0	0	0
T3	1	0	0	0
T4	252	251	0	0
T5	90	89	0	0
T6	0	1	0	0
T16	0	37	0	0
T27	1	0	0	0
T28	3	2	0	0
T29	1	0	0	0
T30	174	173	0	0
T31	1	0	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	50	0	0	0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T24,T25,T26

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T36,T37,T38
1	1	Covered	T24,T25,T26

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4353487	4351374	0	0
selKnown1	29	0	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4353487	4351374	0	0
T1	3928	3927	0	0
T2	6	5	0	0
T3	6	5	0	0
T4	9488	9487	0	0
T5	21032	21031	0	0
T27	6	5	0	0
T28	93	92	0	0
T29	6	5	0	0
T30	5144	5143	0	0
T31	6	5	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	29	0	0	0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T26,T36,T39

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T26,T36,T39
1	0	Covered	T24,T25,T37
1	1	Covered	T26,T36,T39

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4375187	4372506	0	0
selKnown1	23	0	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4375187	4372506	0	0
T1	3949	3948	0	0
T2	7	6	0	0
T3	7	6	0	0
T4	9537	9536	0	0
T5	21048	21047	0	0
T27	7	6	0	0
T28	92	91	0	0
T29	7	6	0	0
T30	5181	5180	0	0
T31	0	6	0	0
T35	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	23	0	0	0