Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15975788	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16741161	1		T1	6		T2	20		T3	37

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32122258	1		T1	4		T2	15		T3	61
values[0x0]	296559	1		T1	6		T2	11		T3	18
values[0x1]	298132	1		T1	3		T2	8		T3	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12740354	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19976595	1		T1	7		T2	24		T3	57

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	309123	1		T30	3		T8	2		T41	11
valid_sources[0x01]	94369	1		T19	1		T30	165		T41	16
valid_sources[0x02]	433509	1		T3	2		T8	2		T41	17
valid_sources[0x03]	93409	1		T19	1		T23	1		T30	8
valid_sources[0x04]	97249	1		T19	1		T23	1		T30	1
valid_sources[0x05]	96770	1		T7	5		T30	38		T10	1
valid_sources[0x06]	94487	1		T3	3		T41	41		T10	1
valid_sources[0x07]	156719	1		T1	13		T30	137		T41	24
valid_sources[0x08]	92707	1		T3	1		T19	1		T30	2
valid_sources[0x09]	95455	1		T18	69		T19	1		T30	5
valid_sources[0x0a]	93836	1		T30	2		T8	1		T41	42
valid_sources[0x0b]	97817	1		T30	4		T8	2		T41	8
valid_sources[0x0c]	92872	1		T3	1		T30	1		T41	5
valid_sources[0x0d]	138818	1		T3	2		T30	1		T8	1
valid_sources[0x0e]	260610	1		T30	2		T8	1		T41	32
valid_sources[0x0f]	95516	1		T8	2		T41	1		T10	1
valid_sources[0x10]	93644	1		T30	3		T8	1		T41	6
valid_sources[0x11]	140473	1		T2	2		T19	1		T41	56
valid_sources[0x12]	93949	1		T30	1		T41	3		T10	1
valid_sources[0x13]	94247	1		T30	2		T8	1		T41	30
valid_sources[0x14]	94557	1		T30	256		T41	7		T10	2
valid_sources[0x15]	93375	1		T7	1		T30	2		T8	2
valid_sources[0x16]	95288	1		T3	1		T30	4		T41	32
valid_sources[0x17]	92738	1		T3	1		T30	1		T41	30
valid_sources[0x18]	182026	1		T30	4		T8	3		T9	4
valid_sources[0x19]	312571	1		T30	3		T41	35		T9	1
valid_sources[0x1a]	96443	1		T3	2		T8	1		T41	15
valid_sources[0x1b]	94058	1		T30	3		T106	2		T9	2
valid_sources[0x1c]	117562	1		T3	3		T7	2		T23	1
valid_sources[0x1d]	93595	1		T7	8		T20	1		T30	53
valid_sources[0x1e]	216237	1		T2	2		T23	1		T8	1
valid_sources[0x1f]	121295	1		T30	4		T8	2		T41	23
valid_sources[0x20]	94610	1		T30	2		T41	3		T13	1
valid_sources[0x21]	94786	1		T8	1		T10	3		T4	105
valid_sources[0x22]	94905	1		T30	12		T8	1		T41	25
valid_sources[0x23]	95183	1		T2	1		T30	3		T98	6
valid_sources[0x24]	93137	1		T30	1		T8	1		T41	16
valid_sources[0x25]	287646	1		T19	1		T30	3		T41	32
valid_sources[0x26]	273003	1		T3	1		T30	2		T9	2
valid_sources[0x27]	221517	1		T30	5		T8	1		T41	1
valid_sources[0x28]	93517	1		T19	1		T30	26		T9	1
valid_sources[0x29]	118322	1		T30	5		T13	2		T4	78
valid_sources[0x2a]	95052	1		T30	2		T8	1		T41	14
valid_sources[0x2b]	94194	1		T3	2		T30	4		T41	14
valid_sources[0x2c]	111913	1		T23	1		T30	3		T41	29
valid_sources[0x2d]	275263	1		T3	4		T7	2		T30	165
valid_sources[0x2e]	251911	1		T2	1		T7	1		T20	1
valid_sources[0x2f]	99898	1		T30	1		T41	22		T9	2
valid_sources[0x30]	95632	1		T8	3		T41	9		T12	1
valid_sources[0x31]	353578	1		T19	1		T30	128		T8	1
valid_sources[0x32]	134014	1		T30	2		T41	17		T10	2
valid_sources[0x33]	92878	1		T3	1		T30	4		T8	1
valid_sources[0x34]	96955	1		T30	39		T41	11		T10	2
valid_sources[0x35]	93535	1		T30	4		T41	27		T4	119
valid_sources[0x36]	117393	1		T7	1		T30	6		T8	1
valid_sources[0x37]	112075	1		T19	1		T41	33		T4	100
valid_sources[0x38]	383810	1		T3	1		T30	2		T8	1
valid_sources[0x39]	95306	1		T30	139		T41	16		T99	1
valid_sources[0x3a]	97825	1		T30	4		T8	1		T41	14
valid_sources[0x3b]	94517	1		T30	3		T41	37		T9	1
valid_sources[0x3c]	93382	1		T3	2		T25	1		T41	14
valid_sources[0x3d]	94802	1		T19	1		T8	2		T41	6
valid_sources[0x3e]	94398	1		T19	1		T30	26		T8	1
valid_sources[0x3f]	91038	1		T30	2		T41	11		T4	87
valid_sources[0x40]	130147	1		T30	1		T41	25		T9	1
valid_sources[0x41]	97031	1		T30	2		T8	1		T41	60
valid_sources[0x42]	95398	1		T30	3		T41	14		T9	1
valid_sources[0x43]	94316	1		T30	3		T98	1		T41	12
valid_sources[0x44]	111929	1		T30	271		T41	4		T4	95
valid_sources[0x45]	95128	1		T30	3		T41	14		T9	1
valid_sources[0x46]	221598	1		T30	19		T9	1		T10	1
valid_sources[0x47]	93171	1		T3	3		T20	1		T30	2
valid_sources[0x48]	94374	1		T3	1		T30	644		T8	1
valid_sources[0x49]	363029	1		T3	3		T30	4		T98	2
valid_sources[0x4a]	147023	1		T3	6		T30	1		T41	21
valid_sources[0x4b]	127805	1		T23	3		T8	3		T41	22
valid_sources[0x4c]	92829	1		T2	2		T234	4		T41	5
valid_sources[0x4d]	92954	1		T30	1		T8	1		T41	1
valid_sources[0x4e]	93453	1		T30	430		T41	7		T10	1
valid_sources[0x4f]	269629	1		T19	1		T30	3		T41	35
valid_sources[0x50]	95508	1		T41	8		T9	6		T13	3
valid_sources[0x51]	106883	1		T30	3		T41	5		T4	95
valid_sources[0x52]	124525	1		T17	242		T30	1		T9	2
valid_sources[0x53]	117282	1		T21	307		T30	4		T8	2
valid_sources[0x54]	95016	1		T19	1		T30	6		T41	27
valid_sources[0x55]	114607	1		T2	1		T29	1		T30	1
valid_sources[0x56]	186313	1		T30	7		T234	1		T41	1
valid_sources[0x57]	94127	1		T30	4		T8	1		T41	15
valid_sources[0x58]	95871	1		T19	1		T30	2		T9	4
valid_sources[0x59]	93876	1		T30	3		T13	3		T4	121
valid_sources[0x5a]	164999	1		T2	1		T30	3		T8	1
valid_sources[0x5b]	94695	1		T3	1		T30	2		T41	62
valid_sources[0x5c]	94760	1		T30	140		T8	1		T41	70
valid_sources[0x5d]	94158	1		T3	2		T19	1		T30	7
valid_sources[0x5e]	285348	1		T30	1		T8	1		T41	12
valid_sources[0x5f]	93522	1		T20	1		T41	54		T4	104
valid_sources[0x60]	127228	1		T30	4		T9	1		T4	97
valid_sources[0x61]	93886	1		T7	6		T19	1		T30	4
valid_sources[0x62]	113975	1		T30	262		T8	1		T41	31
valid_sources[0x63]	313329	1		T30	2		T8	1		T4	102
valid_sources[0x64]	94891	1		T30	2		T8	1		T41	6
valid_sources[0x65]	95077	1		T30	1		T8	4		T41	3
valid_sources[0x66]	189024	1		T9	1		T10	1		T4	107
valid_sources[0x67]	114891	1		T23	1		T30	2		T8	1
valid_sources[0x68]	95576	1		T30	2		T40	1		T13	1
valid_sources[0x69]	95185	1		T30	4		T8	1		T41	17
valid_sources[0x6a]	108848	1		T19	1		T41	57		T10	1
valid_sources[0x6b]	113288	1		T30	231		T4	93		T37	101
valid_sources[0x6c]	94884	1		T3	4		T41	23		T10	1
valid_sources[0x6d]	138866	1		T41	9		T4	83		T37	19
valid_sources[0x6e]	129068	1		T8	1		T41	6		T9	1
valid_sources[0x6f]	337581	1		T8	1		T41	42		T13	3
valid_sources[0x70]	93905	1		T25	3		T30	3		T41	10
valid_sources[0x71]	93501	1		T2	1		T3	2		T24	11
valid_sources[0x72]	95239	1		T30	2		T4	87		T37	28
valid_sources[0x73]	137165	1		T7	2		T30	75		T41	16
valid_sources[0x74]	92661	1		T20	1		T25	1		T29	1
valid_sources[0x75]	95126	1		T30	2		T41	21		T10	3
valid_sources[0x76]	95588	1		T30	4		T8	2		T41	28
valid_sources[0x77]	94224	1		T19	1		T8	2		T98	1
valid_sources[0x78]	93691	1		T30	2		T41	39		T10	1
valid_sources[0x79]	117454	1		T20	1		T30	4		T41	1
valid_sources[0x7a]	122460	1		T7	4		T30	4		T41	7
valid_sources[0x7b]	93502	1		T30	3		T41	19		T99	1
valid_sources[0x7c]	97311	1		T7	1		T29	2		T30	56
valid_sources[0x7d]	96094	1		T30	1		T41	21		T13	3
valid_sources[0x7e]	94294	1		T2	1		T30	1		T41	6
valid_sources[0x7f]	114030	1		T30	2		T98	2		T41	35
valid_sources[0x80]	95050	1		T30	2		T41	12		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16270853

1

T1

1

T2

8

T3

4

values[0x0]

all_enables

biggest_size

242699

1

T1

4

T2

9

T3

13

values[0x1]

all_enables

biggest_size

227609

1

T1

1

T2

3

T3

20