Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	15990818	1		T1	7		T2	14		T3	67
full_word	16742311	1		T1	6		T2	20		T3	37

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32732829	1		T1	13		T2	34		T3	104
auto[TlIntgErrCmd]	116	1		T184	10		T218	4		T219	7
auto[TlIntgErrData]	91	1		T184	7		T218	1		T219	5
auto[TlIntgErrBoth]	93	1		T184	3		T218	5		T219	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32124320	1		T1	4		T2	15		T3	61
auto[1]	608809	1		T1	9		T2	19		T3	43

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15853132	1		T1	3		T2	7		T3	57
auto[TlIntgErrNone]	partial	auto[1]	137415	1		T1	4		T2	7		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	16271037	1		T1	1		T2	8		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	471245	1		T1	5		T2	12		T3	33
auto[TlIntgErrCmd]	partial	auto[0]	47	1		T184	1		T218	2		T219	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1		T184	8		T218	2		T219	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T291	1		T296	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T184	1		T291	1		T297	2
auto[TlIntgErrData]	partial	auto[0]	44	1		T184	2		T219	3		T298	1
auto[TlIntgErrData]	partial	auto[1]	37	1		T184	4		T218	1		T219	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T292	1		T293	1		T299	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T184	1		T291	1		T293	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1		T184	2		T218	2		T219	2
auto[TlIntgErrBoth]	partial	auto[1]	38	1		T184	1		T218	3		T219	5
auto[TlIntgErrBoth]	full_word	auto[0]	8	1		T298	1		T292	2		T293	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T219	1		T293	1		T297	1