Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	506226726	12171	0	0
ep_in_enable_rd_A	506226726	3527	0	0
ep_out_enable_rd_A	506226726	3438	0	0
in_iso_rd_A	506226726	3184	0	0
intr_enable_rd_A	506226726	4715	0	0
out_iso_rd_A	506226726	3580	0	0
phy_config_rd_A	506226726	2340	0	0
phy_pins_drive_rd_A	506226726	3146	0	0
rxenable_setup_rd_A	506226726	3323	0	0
set_nak_out_rd_A	506226726	3663	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506226726	12171	0	0
T184	34353	10	0	0
T185	16105	815	0	0
T186	2714	283	0	0
T213	5830	197	0	0
T225	7315	341	0	0
T227	4045	13	0	0
T228	7583	11	0	0
T230	8855	20	0	0
T232	8133	10	0	0
T233	7258	10	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506226726	3527	0	0
T190	12437	55	0	0
T219	48012	634	0	0
T230	8855	24	0	0
T232	8133	18	0	0
T233	7258	3	0	0
T254	10613	38	0	0
T257	11351	19	0	0
T265	12082	58	0	0
T266	10966	32	0	0
T267	48304	91	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506226726	3438	0	0
T190	12437	34	0	0
T219	48012	510	0	0
T230	8855	38	0	0
T232	8133	56	0	0
T233	7258	2	0	0
T254	10613	51	0	0
T257	11351	46	0	0
T265	12082	66	0	0
T266	10966	49	0	0
T267	48304	188	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506226726	3184	0	0
T190	12437	41	0	0
T219	48012	340	0	0
T230	8855	29	0	0
T233	7258	55	0	0
T247	4595	109	0	0
T254	10613	26	0	0
T257	11351	39	0	0
T265	12082	4	0	0
T266	10966	31	0	0
T267	48304	117	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506226726	4715	0	0
T190	12437	56	0	0
T195	3057	11	0	0
T197	2187	28	0	0
T200	3416	14	0	0
T230	8855	35	0	0
T232	8133	102	0	0
T233	7258	11	0	0
T254	10613	12	0	0
T257	11351	62	0	0
T265	12082	76	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506226726	3580	0	0
T190	12437	74	0	0
T219	48012	325	0	0
T230	8855	46	0	0
T232	8133	43	0	0
T233	7258	49	0	0
T254	10613	21	0	0
T257	11351	51	0	0
T265	12082	111	0	0
T266	10966	22	0	0
T267	48304	80	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506226726	2340	0	0
T190	12437	11	0	0
T219	48012	282	0	0
T230	8855	18	0	0
T232	8133	13	0	0
T233	7258	32	0	0
T254	10613	59	0	0
T257	11351	58	0	0
T265	12082	60	0	0
T266	10966	15	0	0
T267	48304	65	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506226726	3146	0	0
T190	12437	43	0	0
T219	48012	331	0	0
T230	8855	10	0	0
T232	8133	32	0	0
T233	7258	32	0	0
T254	10613	43	0	0
T257	11351	66	0	0
T265	12082	51	0	0
T266	10966	23	0	0
T267	48304	77	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506226726	3323	0	0
T190	12437	67	0	0
T219	48012	494	0	0
T230	8855	29	0	0
T232	8133	30	0	0
T233	7258	67	0	0
T254	10613	15	0	0
T257	11351	35	0	0
T265	12082	50	0	0
T266	10966	15	0	0
T267	48304	169	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506226726	3663	0	0
T190	12437	49	0	0
T219	48012	555	0	0
T230	8855	32	0	0
T232	8133	52	0	0
T233	7258	15	0	0
T254	10613	16	0	0
T257	11351	63	0	0
T265	12082	7	0	0
T266	10966	25	0	0
T267	48304	71	0	0