Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15960537	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16786967	1		T1	23		T2	11		T3	22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32107344	1		T1	21		T2	9		T3	22
values[0x0]	319084	1		T1	2		T2	2		T3	5
values[0x1]	321076	1		T1	5		T2	6		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12727794	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20019710	1		T1	24		T2	12		T3	24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	97570	1		T4	322		T5	334		T6	99
valid_sources[0x01]	96131	1		T4	375		T5	323		T6	84
valid_sources[0x02]	96789	1		T3	1		T4	344		T5	390
valid_sources[0x03]	132666	1		T4	330		T5	364		T6	101
valid_sources[0x04]	99325	1		T4	320		T5	352		T6	98
valid_sources[0x05]	98579	1		T3	2		T4	332		T5	349
valid_sources[0x06]	96770	1		T4	331		T5	349		T6	112
valid_sources[0x07]	98706	1		T4	333		T5	363		T6	96
valid_sources[0x08]	107674	1		T4	343		T5	383		T6	85
valid_sources[0x09]	97022	1		T4	341		T5	372		T6	108
valid_sources[0x0a]	96284	1		T4	374		T5	359		T6	116
valid_sources[0x0b]	96435	1		T28	23		T4	363		T5	352
valid_sources[0x0c]	98008	1		T4	354		T5	339		T6	94
valid_sources[0x0d]	98470	1		T4	315		T5	399		T6	107
valid_sources[0x0e]	118975	1		T3	1		T4	324		T5	365
valid_sources[0x0f]	97904	1		T29	9		T4	368		T5	357
valid_sources[0x10]	96793	1		T4	381		T5	339		T6	99
valid_sources[0x11]	126375	1		T4	347		T5	344		T6	118
valid_sources[0x12]	96371	1		T4	326		T5	308		T6	135
valid_sources[0x13]	98942	1		T4	318		T5	352		T6	104
valid_sources[0x14]	96834	1		T3	1		T4	382		T5	337
valid_sources[0x15]	110487	1		T4	307		T5	353		T6	94
valid_sources[0x16]	97670	1		T4	318		T5	335		T6	121
valid_sources[0x17]	265971	1		T4	318		T5	368		T6	111
valid_sources[0x18]	99614	1		T4	313		T5	334		T6	129
valid_sources[0x19]	96883	1		T3	2		T4	316		T5	328
valid_sources[0x1a]	96950	1		T4	292		T5	336		T6	108
valid_sources[0x1b]	126752	1		T4	340		T5	354		T6	105
valid_sources[0x1c]	367464	1		T3	4		T4	349		T5	409
valid_sources[0x1d]	303648	1		T4	417		T5	358		T6	101
valid_sources[0x1e]	98997	1		T4	397		T5	361		T6	118
valid_sources[0x1f]	98021	1		T2	1		T4	324		T5	352
valid_sources[0x20]	234678	1		T4	253		T5	315		T6	116
valid_sources[0x21]	118003	1		T4	347		T5	336		T6	111
valid_sources[0x22]	97438	1		T4	343		T5	394		T6	131
valid_sources[0x23]	98936	1		T4	333		T35	1		T5	377
valid_sources[0x24]	97998	1		T3	2		T4	345		T5	367
valid_sources[0x25]	231393	1		T4	344		T5	384		T6	123
valid_sources[0x26]	97322	1		T4	378		T5	335		T6	83
valid_sources[0x27]	95802	1		T30	8		T4	289		T5	343
valid_sources[0x28]	97490	1		T4	319		T5	370		T6	102
valid_sources[0x29]	97074	1		T4	304		T5	372		T6	96
valid_sources[0x2a]	128679	1		T4	326		T5	341		T6	107
valid_sources[0x2b]	98820	1		T4	332		T5	344		T6	81
valid_sources[0x2c]	98294	1		T34	1		T4	302		T5	349
valid_sources[0x2d]	98038	1		T4	397		T5	352		T6	130
valid_sources[0x2e]	322190	1		T4	379		T5	334		T6	102
valid_sources[0x2f]	99817	1		T4	310		T5	362		T6	100
valid_sources[0x30]	113606	1		T2	3		T4	334		T5	384
valid_sources[0x31]	94913	1		T4	292		T5	353		T6	135
valid_sources[0x32]	96674	1		T2	1		T4	299		T5	338
valid_sources[0x33]	98170	1		T4	297		T5	338		T6	102
valid_sources[0x34]	157982	1		T4	333		T5	338		T6	98
valid_sources[0x35]	97880	1		T4	326		T5	333		T6	109
valid_sources[0x36]	97049	1		T4	368		T5	327		T6	112
valid_sources[0x37]	137560	1		T4	346		T35	1		T5	341
valid_sources[0x38]	98045	1		T4	341		T5	363		T6	100
valid_sources[0x39]	97277	1		T4	314		T5	336		T6	137
valid_sources[0x3a]	97351	1		T4	355		T5	384		T6	101
valid_sources[0x3b]	98736	1		T4	353		T5	377		T6	113
valid_sources[0x3c]	97078	1		T4	397		T5	340		T6	80
valid_sources[0x3d]	98297	1		T3	3		T4	344		T5	363
valid_sources[0x3e]	101589	1		T3	1		T4	365		T5	364
valid_sources[0x3f]	96064	1		T34	2		T4	399		T5	317
valid_sources[0x40]	239247	1		T4	350		T5	364		T6	97
valid_sources[0x41]	97637	1		T4	348		T5	397		T6	108
valid_sources[0x42]	97594	1		T2	1		T4	365		T5	370
valid_sources[0x43]	97228	1		T4	349		T5	349		T6	106
valid_sources[0x44]	100159	1		T4	338		T5	373		T6	98
valid_sources[0x45]	97371	1		T4	281		T5	348		T6	104
valid_sources[0x46]	106955	1		T4	351		T5	374		T6	105
valid_sources[0x47]	96305	1		T2	2		T4	307		T5	411
valid_sources[0x48]	101482	1		T4	346		T5	375		T6	125
valid_sources[0x49]	439990	1		T4	278		T5	360		T6	139
valid_sources[0x4a]	128163	1		T2	1		T3	1		T4	336
valid_sources[0x4b]	98292	1		T4	355		T5	359		T6	94
valid_sources[0x4c]	343782	1		T4	367		T5	381		T6	117
valid_sources[0x4d]	97400	1		T4	311		T5	388		T6	86
valid_sources[0x4e]	96343	1		T4	358		T5	354		T6	109
valid_sources[0x4f]	256458	1		T4	301		T5	308		T6	100
valid_sources[0x50]	98417	1		T4	302		T5	321		T6	112
valid_sources[0x51]	96518	1		T34	2		T4	303		T5	375
valid_sources[0x52]	190948	1		T4	341		T5	375		T6	126
valid_sources[0x53]	122946	1		T2	1		T4	345		T5	353
valid_sources[0x54]	98408	1		T4	304		T5	330		T6	115
valid_sources[0x55]	99413	1		T3	1		T4	275		T5	360
valid_sources[0x56]	100159	1		T3	2		T4	314		T5	341
valid_sources[0x57]	97598	1		T2	1		T4	304		T5	359
valid_sources[0x58]	97856	1		T4	298		T5	334		T6	108
valid_sources[0x59]	97452	1		T3	1		T4	357		T5	326
valid_sources[0x5a]	122138	1		T4	323		T35	1		T5	387
valid_sources[0x5b]	97812	1		T4	319		T5	358		T6	111
valid_sources[0x5c]	95449	1		T4	402		T5	343		T6	121
valid_sources[0x5d]	98274	1		T4	354		T5	355		T6	118
valid_sources[0x5e]	97712	1		T4	314		T5	332		T6	102
valid_sources[0x5f]	97548	1		T4	350		T5	316		T6	109
valid_sources[0x60]	203048	1		T4	354		T5	403		T6	110
valid_sources[0x61]	100628	1		T4	315		T5	285		T6	107
valid_sources[0x62]	128730	1		T4	316		T5	318		T6	122
valid_sources[0x63]	96939	1		T4	348		T5	374		T6	111
valid_sources[0x64]	97751	1		T4	368		T5	353		T6	103
valid_sources[0x65]	97735	1		T4	295		T5	327		T6	90
valid_sources[0x66]	165132	1		T4	312		T5	384		T6	112
valid_sources[0x67]	96473	1		T4	351		T5	362		T6	109
valid_sources[0x68]	99320	1		T4	326		T5	385		T6	80
valid_sources[0x69]	99652	1		T4	293		T5	370		T6	119
valid_sources[0x6a]	97443	1		T4	294		T5	340		T6	113
valid_sources[0x6b]	96616	1		T4	410		T5	359		T6	103
valid_sources[0x6c]	97952	1		T4	348		T5	370		T6	102
valid_sources[0x6d]	96548	1		T4	346		T5	336		T6	108
valid_sources[0x6e]	96045	1		T4	351		T5	325		T6	129
valid_sources[0x6f]	135283	1		T4	382		T5	345		T6	131
valid_sources[0x70]	227190	1		T30	1		T4	358		T5	365
valid_sources[0x71]	302459	1		T4	291		T5	339		T6	94
valid_sources[0x72]	98118	1		T4	301		T5	352		T6	130
valid_sources[0x73]	97735	1		T30	1		T4	317		T5	328
valid_sources[0x74]	126805	1		T4	393		T5	339		T6	112
valid_sources[0x75]	98108	1		T34	2		T4	349		T5	385
valid_sources[0x76]	97509	1		T4	373		T5	315		T6	124
valid_sources[0x77]	98348	1		T4	329		T5	370		T6	100
valid_sources[0x78]	277611	1		T4	374		T5	357		T6	100
valid_sources[0x79]	98312	1		T4	331		T5	383		T6	82
valid_sources[0x7a]	123025	1		T4	315		T5	366		T6	123
valid_sources[0x7b]	140413	1		T4	314		T35	1		T5	351
valid_sources[0x7c]	97534	1		T29	1		T4	365		T5	378
valid_sources[0x7d]	406002	1		T4	369		T5	408		T6	136
valid_sources[0x7e]	98497	1		T4	347		T5	391		T6	109
valid_sources[0x7f]	96199	1		T3	1		T4	384		T5	329
valid_sources[0x80]	97292	1		T34	1		T4	291		T5	376

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16270430

1

T1

19

T2

6

T3

16

values[0x0]

all_enables

biggest_size

265302

1

T1

2

T2

2

T3

3

values[0x1]

all_enables

biggest_size

251235

1

T1

2

T2

3

T3

3