Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	15975215	1		T1	5		T2	6		T3	11
full_word	16787982	1		T1	23		T2	11		T3	22

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32762867	1		T1	28		T2	17		T3	33
auto[TlIntgErrCmd]	105	1		T186	8		T211	11		T220	5
auto[TlIntgErrData]	103	1		T186	6		T211	4		T220	5
auto[TlIntgErrBoth]	122	1		T186	6		T211	5		T220	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32109113	1		T1	21		T2	9		T3	22
auto[1]	654084	1		T1	7		T2	8		T3	11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15838367	1		T1	2		T2	3		T3	6
auto[TlIntgErrNone]	partial	auto[1]	136540	1		T1	3		T2	3		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	16270598	1		T1	19		T2	6		T3	16
auto[TlIntgErrNone]	full_word	auto[1]	517362	1		T1	4		T2	5		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T186	3		T211	4		T220	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T186	5		T211	6		T220	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T295	2		T296	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T211	1		T293	1		T297	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T186	2		T211	3		T220	2
auto[TlIntgErrData]	partial	auto[1]	52	1		T186	3		T220	3		T293	4
auto[TlIntgErrData]	full_word	auto[0]	8	1		T186	1		T268	2		T270	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T211	1		T294	1		T298	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1		T186	3		T211	3		T220	4
auto[TlIntgErrBoth]	partial	auto[1]	66	1		T186	3		T211	2		T220	6
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T298	2		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T298	1		T299	1		-	-