Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	503955946	11816	0	0
ep_in_enable_rd_A	503955946	3059	0	0
ep_out_enable_rd_A	503955946	3141	0	0
in_iso_rd_A	503955946	2987	0	0
intr_enable_rd_A	503955946	4384	0	0
out_iso_rd_A	503955946	2704	0	0
phy_config_rd_A	503955946	2000	0	0
phy_pins_drive_rd_A	503955946	2634	0	0
rxenable_setup_rd_A	503955946	2944	0	0
set_nak_out_rd_A	503955946	3301	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503955946	11816	0	0
T185	4528	8	0	0
T186	23992	4	0	0
T187	4341	501	0	0
T210	6487	4	0	0
T211	34704	7	0	0
T212	7482	12	0	0
T216	5670	748	0	0
T217	14480	865	0	0
T221	5097	17	0	0
T230	5540	6	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503955946	3059	0	0
T210	6487	4	0	0
T220	42475	561	0	0
T228	5403	8	0	0
T244	9122	7	0	0
T248	6358	49	0	0
T261	5840	13	0	0
T266	7276	5	0	0
T267	3896	23	0	0
T268	58212	214	0	0
T269	6952	6	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503955946	3141	0	0
T210	6487	7	0	0
T220	42475	439	0	0
T228	5403	8	0	0
T244	9122	1	0	0
T248	6358	49	0	0
T261	5840	2	0	0
T266	7276	29	0	0
T267	3896	41	0	0
T268	58212	316	0	0
T270	46330	416	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503955946	2987	0	0
T210	6487	49	0	0
T217	14480	1	0	0
T220	42475	416	0	0
T228	5403	4	0	0
T246	2224	22	0	0
T248	6358	52	0	0
T261	5840	13	0	0
T266	7276	55	0	0
T267	3896	78	0	0
T268	58212	132	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503955946	4384	0	0
T197	2046	10	0	0
T198	2159	20	0	0
T210	6487	4	0	0
T220	42475	881	0	0
T228	5403	8	0	0
T244	9122	5	0	0
T271	2805	11	0	0
T272	2009	23	0	0
T273	2184	24	0	0
T274	2152	10	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503955946	2704	0	0
T210	6487	12	0	0
T220	42475	523	0	0
T228	5403	11	0	0
T244	9122	8	0	0
T246	2224	2	0	0
T248	6358	31	0	0
T261	5840	18	0	0
T266	7276	40	0	0
T267	3896	10	0	0
T268	58212	152	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503955946	2000	0	0
T210	6487	3	0	0
T220	42475	288	0	0
T228	5403	4	0	0
T244	9122	5	0	0
T246	2224	10	0	0
T248	6358	1	0	0
T266	7276	9	0	0
T267	3896	11	0	0
T268	58212	103	0	0
T269	6952	7	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503955946	2634	0	0
T210	6487	33	0	0
T220	42475	344	0	0
T228	5403	34	0	0
T244	9122	5	0	0
T246	2224	14	0	0
T248	6358	32	0	0
T261	5840	8	0	0
T266	7276	36	0	0
T268	58212	272	0	0
T269	6952	1	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503955946	2944	0	0
T210	6487	41	0	0
T220	42475	712	0	0
T228	5403	11	0	0
T244	9122	2	0	0
T248	6358	38	0	0
T261	5840	18	0	0
T266	7276	4	0	0
T267	3896	15	0	0
T268	58212	328	0	0
T269	6952	14	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503955946	3301	0	0
T217	14480	4	0	0
T220	42475	618	0	0
T228	5403	5	0	0
T244	9122	4	0	0
T246	2224	6	0	0
T261	5840	16	0	0
T266	7276	64	0	0
T267	3896	60	0	0
T268	58212	401	0	0
T270	46330	255	0	0