Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15460582	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16284855	1		T1	15		T2	5		T3	150

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31107739	1		T1	274		T2	2		T3	111
values[0x0]	318189	1		T1	8		T2	2		T3	50
values[0x1]	319509	1		T1	13		T2	6		T3	53

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12325543	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19419894	1		T1	105		T2	7		T3	165

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	98995	1		T5	139		T28	63		T29	5
valid_sources[0x01]	99793	1		T16	1		T22	8		T5	182
valid_sources[0x02]	109629	1		T16	2		T5	171		T28	78
valid_sources[0x03]	98907	1		T16	1		T19	3		T5	155
valid_sources[0x04]	204940	1		T16	3		T19	1		T5	174
valid_sources[0x05]	98799	1		T5	161		T28	78		T40	31
valid_sources[0x06]	98031	1		T19	1		T5	149		T28	60
valid_sources[0x07]	97359	1		T16	2		T17	1		T5	187
valid_sources[0x08]	241517	1		T16	2		T19	2		T5	136
valid_sources[0x09]	97415	1		T16	2		T5	152		T28	115
valid_sources[0x0a]	113698	1		T16	3		T19	1		T5	153
valid_sources[0x0b]	98690	1		T5	135		T28	141		T40	37
valid_sources[0x0c]	98016	1		T16	1		T5	190		T28	102
valid_sources[0x0d]	98637	1		T16	2		T20	1		T5	132
valid_sources[0x0e]	97440	1		T16	4		T19	1		T20	4
valid_sources[0x0f]	96421	1		T16	7		T19	1		T5	170
valid_sources[0x10]	97691	1		T16	1		T5	130		T28	122
valid_sources[0x11]	280041	1		T16	2		T5	101		T28	89
valid_sources[0x12]	151873	1		T16	2		T5	154		T28	95
valid_sources[0x13]	116649	1		T21	5		T5	193		T28	112
valid_sources[0x14]	97380	1		T16	3		T19	1		T22	4
valid_sources[0x15]	99130	1		T16	3		T5	138		T28	130
valid_sources[0x16]	98804	1		T5	213		T28	82		T40	17
valid_sources[0x17]	99081	1		T16	3		T5	145		T28	71
valid_sources[0x18]	335076	1		T19	3		T5	157		T28	100
valid_sources[0x19]	99399	1		T5	174		T28	83		T29	18
valid_sources[0x1a]	206764	1		T16	6		T5	188		T28	84
valid_sources[0x1b]	98631	1		T16	3		T5	146		T28	93
valid_sources[0x1c]	97462	1		T16	3		T5	166		T28	56
valid_sources[0x1d]	336409	1		T16	1		T5	140		T28	72
valid_sources[0x1e]	98903	1		T16	1		T5	93		T28	66
valid_sources[0x1f]	97005	1		T5	127		T28	100		T40	21
valid_sources[0x20]	97640	1		T16	3		T5	140		T28	112
valid_sources[0x21]	162511	1		T16	1		T5	111		T28	86
valid_sources[0x22]	98710	1		T16	2		T20	1		T5	163
valid_sources[0x23]	97484	1		T16	1		T5	138		T28	99
valid_sources[0x24]	254994	1		T16	3		T5	127		T28	125
valid_sources[0x25]	97356	1		T16	2		T19	2		T5	139
valid_sources[0x26]	98682	1		T5	168		T27	1		T28	92
valid_sources[0x27]	140277	1		T16	5		T20	2		T5	142
valid_sources[0x28]	99043	1		T16	2		T19	1		T5	112
valid_sources[0x29]	285832	1		T16	2		T5	143		T28	87
valid_sources[0x2a]	97124	1		T5	151		T28	91		T29	17
valid_sources[0x2b]	96683	1		T5	173		T28	70		T40	16
valid_sources[0x2c]	96987	1		T16	7		T5	149		T28	123
valid_sources[0x2d]	97316	1		T16	1		T19	1		T5	153
valid_sources[0x2e]	96617	1		T19	1		T5	168		T28	49
valid_sources[0x2f]	98897	1		T5	129		T28	66		T40	12
valid_sources[0x30]	99294	1		T16	1		T5	181		T28	101
valid_sources[0x31]	98334	1		T16	3		T5	141		T28	120
valid_sources[0x32]	96815	1		T22	1		T5	211		T28	57
valid_sources[0x33]	98826	1		T16	1		T5	126		T28	56
valid_sources[0x34]	99414	1		T16	3		T5	123		T28	71
valid_sources[0x35]	120811	1		T16	1		T19	1		T20	1
valid_sources[0x36]	98220	1		T5	131		T28	96		T40	10
valid_sources[0x37]	97528	1		T16	2		T19	2		T5	117
valid_sources[0x38]	97623	1		T17	1		T5	199		T28	78
valid_sources[0x39]	98362	1		T19	1		T5	185		T28	111
valid_sources[0x3a]	119177	1		T16	1		T5	155		T28	98
valid_sources[0x3b]	98401	1		T16	4		T5	165		T28	95
valid_sources[0x3c]	128400	1		T16	2		T5	106		T28	80
valid_sources[0x3d]	97998	1		T16	1		T5	154		T28	71
valid_sources[0x3e]	189574	1		T5	175		T28	88		T29	4
valid_sources[0x3f]	98151	1		T16	2		T5	161		T28	102
valid_sources[0x40]	257028	1		T16	1		T5	136		T28	115
valid_sources[0x41]	156784	1		T19	1		T5	126		T28	64
valid_sources[0x42]	97398	1		T19	1		T5	121		T28	75
valid_sources[0x43]	98772	1		T5	174		T28	85		T40	24
valid_sources[0x44]	99934	1		T16	4		T19	1		T5	114
valid_sources[0x45]	192217	1		T5	181		T28	69		T29	1
valid_sources[0x46]	98710	1		T16	1		T19	1		T5	128
valid_sources[0x47]	160454	1		T26	11		T5	155		T28	71
valid_sources[0x48]	97712	1		T1	295		T21	5		T22	1
valid_sources[0x49]	123738	1		T5	128		T28	80		T40	26
valid_sources[0x4a]	186731	1		T5	120		T28	142		T40	25
valid_sources[0x4b]	98368	1		T16	4		T5	136		T28	60
valid_sources[0x4c]	231656	1		T16	3		T5	158		T28	79
valid_sources[0x4d]	97739	1		T16	1		T5	124		T28	80
valid_sources[0x4e]	99864	1		T16	2		T5	186		T28	117
valid_sources[0x4f]	97163	1		T16	7		T19	1		T20	1
valid_sources[0x50]	127207	1		T16	3		T5	156		T28	68
valid_sources[0x51]	272536	1		T5	150		T28	104		T40	21
valid_sources[0x52]	97845	1		T16	1		T19	1		T5	135
valid_sources[0x53]	164160	1		T16	2		T5	120		T28	121
valid_sources[0x54]	129068	1		T16	1		T5	172		T28	84
valid_sources[0x55]	97934	1		T16	2		T5	162		T28	86
valid_sources[0x56]	98247	1		T20	2		T5	116		T28	45
valid_sources[0x57]	98803	1		T16	1		T5	145		T28	102
valid_sources[0x58]	97170	1		T16	1		T5	167		T28	86
valid_sources[0x59]	96422	1		T16	2		T5	167		T28	77
valid_sources[0x5a]	260951	1		T4	134854		T5	160		T28	92
valid_sources[0x5b]	168757	1		T16	5		T5	159		T28	92
valid_sources[0x5c]	97521	1		T5	167		T28	90		T29	4
valid_sources[0x5d]	97934	1		T16	1		T19	1		T5	170
valid_sources[0x5e]	128202	1		T16	1		T5	120		T28	85
valid_sources[0x5f]	231183	1		T5	153		T28	53		T40	26
valid_sources[0x60]	122576	1		T16	2		T5	177		T28	84
valid_sources[0x61]	98262	1		T5	154		T28	106		T29	25
valid_sources[0x62]	109264	1		T16	3		T5	153		T28	77
valid_sources[0x63]	97449	1		T16	2		T19	1		T5	113
valid_sources[0x64]	98769	1		T5	125		T28	104		T40	14
valid_sources[0x65]	98296	1		T16	1		T19	1		T5	157
valid_sources[0x66]	237179	1		T19	1		T5	162		T28	99
valid_sources[0x67]	98717	1		T5	167		T27	1		T28	75
valid_sources[0x68]	98857	1		T16	1		T5	148		T28	106
valid_sources[0x69]	98159	1		T16	2		T5	196		T28	131
valid_sources[0x6a]	96767	1		T16	2		T19	2		T5	172
valid_sources[0x6b]	98182	1		T16	2		T19	1		T5	148
valid_sources[0x6c]	115301	1		T16	1		T5	92		T28	151
valid_sources[0x6d]	96899	1		T5	166		T28	58		T40	33
valid_sources[0x6e]	99445	1		T5	198		T28	66		T40	39
valid_sources[0x6f]	258137	1		T16	1		T5	156		T28	71
valid_sources[0x70]	242936	1		T5	249		T28	99		T40	39
valid_sources[0x71]	144671	1		T5	170		T28	91		T40	23
valid_sources[0x72]	97709	1		T16	2		T5	227		T28	80
valid_sources[0x73]	215551	1		T16	2		T17	1		T20	2
valid_sources[0x74]	99384	1		T16	1		T19	3		T5	156
valid_sources[0x75]	98360	1		T16	2		T5	150		T28	97
valid_sources[0x76]	98315	1		T16	2		T19	1		T5	114
valid_sources[0x77]	197476	1		T16	2		T19	1		T5	159
valid_sources[0x78]	133481	1		T16	4		T5	210		T28	99
valid_sources[0x79]	97453	1		T16	1		T5	166		T27	1
valid_sources[0x7a]	97188	1		T5	108		T28	62		T40	28
valid_sources[0x7b]	99377	1		T3	214		T16	2		T17	1
valid_sources[0x7c]	130410	1		T16	1		T20	1		T5	207
valid_sources[0x7d]	98628	1		T19	2		T5	160		T27	1
valid_sources[0x7e]	99340	1		T20	1		T5	147		T28	85
valid_sources[0x7f]	97530	1		T16	6		T5	182		T28	94
valid_sources[0x80]	129271	1		T16	3		T5	171		T28	97

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15772917

1

T1

2

T2

2

T3

92

values[0x0]

all_enables

biggest_size

263443

1

T1

7

T2

1

T3

31

values[0x1]

all_enables

biggest_size

248495

1

T1

6

T2

2

T3

27