Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	15477377	1		T1	280		T2	5		T3	64
full_word	16285980	1		T1	15		T2	5		T3	150

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31763037	1		T1	295		T2	10		T3	214
auto[TlIntgErrCmd]	121	1		T190	4		T192	6		T213	6
auto[TlIntgErrData]	106	1		T190	9		T192	4		T213	8
auto[TlIntgErrBoth]	93	1		T190	7		T213	6		T226	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31109875	1		T1	274		T2	2		T3	111
auto[1]	653482	1		T1	21		T2	8		T3	103

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15336620	1		T1	272		T3	19		T16	28
auto[TlIntgErrNone]	partial	auto[1]	140466	1		T1	8		T2	5		T3	45
auto[TlIntgErrNone]	full_word	auto[0]	15773105	1		T1	2		T2	2		T3	92
auto[TlIntgErrNone]	full_word	auto[1]	512846	1		T1	13		T2	3		T3	58
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T190	1		T192	3		T213	1
auto[TlIntgErrCmd]	partial	auto[1]	66	1		T190	3		T192	2		T213	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T284	2		T285	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T192	1		T261	1		T286	1
auto[TlIntgErrData]	partial	auto[0]	58	1		T190	7		T192	2		T213	5
auto[TlIntgErrData]	partial	auto[1]	40	1		T192	2		T213	3		T226	5
auto[TlIntgErrData]	full_word	auto[0]	6	1		T190	2		T287	1		T288	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T286	1		T284	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T190	2		T213	2		T226	4
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T190	5		T213	4		T226	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T286	1		T289	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T226	2		T260	1		T261	1