Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	511811000	13214	0	0
ep_in_enable_rd_A	511811000	4721	0	0
ep_out_enable_rd_A	511811000	5146	0	0
in_iso_rd_A	511811000	4938	0	0
intr_enable_rd_A	511811000	7259	0	0
out_iso_rd_A	511811000	4864	0	0
phy_config_rd_A	511811000	3462	0	0
phy_pins_drive_rd_A	511811000	3789	0	0
rxenable_setup_rd_A	511811000	4340	0	0
set_nak_out_rd_A	511811000	5050	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511811000	13214	0	0
T189	5796	6	0	0
T190	56774	3	0	0
T191	3252	10	0	0
T192	19662	1	0	0
T209	6689	359	0	0
T213	50283	5	0	0
T214	5127	814	0	0
T215	10579	23	0	0
T217	14410	873	0	0
T226	43489	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511811000	4721	0	0
T190	56774	447	0	0
T213	50283	433	0	0
T215	10579	61	0	0
T221	17589	1	0	0
T250	3569	56	0	0
T258	4424	2	0	0
T259	23890	262	0	0
T260	33513	261	0	0
T261	18898	84	0	0
T262	10192	92	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511811000	5146	0	0
T190	56774	492	0	0
T213	50283	525	0	0
T215	10579	49	0	0
T250	3569	39	0	0
T258	4424	39	0	0
T259	23890	327	0	0
T260	33513	302	0	0
T261	18898	166	0	0
T262	10192	14	0	0
T263	7280	26	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511811000	4938	0	0
T190	56774	603	0	0
T213	50283	446	0	0
T215	10579	3	0	0
T250	3569	49	0	0
T258	4424	14	0	0
T259	23890	355	0	0
T260	33513	193	0	0
T261	18898	192	0	0
T262	10192	2	0	0
T263	7280	31	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511811000	7259	0	0
T190	56774	943	0	0
T213	50283	785	0	0
T215	10579	88	0	0
T250	3569	156	0	0
T258	4424	6	0	0
T259	23890	536	0	0
T263	7280	62	0	0
T264	2039	10	0	0
T265	2738	7	0	0
T266	2590	22	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511811000	4864	0	0
T190	56774	373	0	0
T213	50283	522	0	0
T215	10579	81	0	0
T217	14410	9	0	0
T250	3569	7	0	0
T258	4424	14	0	0
T259	23890	306	0	0
T260	33513	228	0	0
T261	18898	164	0	0
T263	7280	42	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511811000	3462	0	0
T190	56774	310	0	0
T213	50283	342	0	0
T215	10579	39	0	0
T250	3569	33	0	0
T258	4424	3	0	0
T259	23890	129	0	0
T260	33513	152	0	0
T261	18898	51	0	0
T262	10192	62	0	0
T263	7280	28	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511811000	3789	0	0
T190	56774	515	0	0
T213	50283	373	0	0
T215	10579	43	0	0
T250	3569	9	0	0
T258	4424	2	0	0
T259	23890	180	0	0
T260	33513	124	0	0
T261	18898	139	0	0
T262	10192	42	0	0
T263	7280	36	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511811000	4340	0	0
T190	56774	446	0	0
T213	50283	495	0	0
T215	10579	55	0	0
T250	3569	58	0	0
T258	4424	3	0	0
T259	23890	187	0	0
T260	33513	148	0	0
T261	18898	160	0	0
T262	10192	80	0	0
T263	7280	6	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	511811000	5050	0	0
T190	56774	515	0	0
T213	50283	637	0	0
T215	10579	20	0	0
T250	3569	85	0	0
T258	4424	41	0	0
T259	23890	254	0	0
T260	33513	276	0	0
T261	18898	159	0	0
T262	10192	30	0	0
T263	7280	48	0	0