Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	374	1		T3	8		T13	5		T5	5
all_values[1]	374	1		T3	8		T13	5		T5	5
all_values[2]	374	1		T3	8		T13	5		T5	5
all_values[3]	374	1		T3	8		T13	5		T5	5
all_values[4]	374	1		T3	8		T13	5		T5	5
all_values[5]	374	1		T3	8		T13	5		T5	5
all_values[6]	374	1		T3	8		T13	5		T5	5
all_values[7]	374	1		T3	8		T13	5		T5	5
all_values[8]	374	1		T3	8		T13	5		T5	5
all_values[9]	374	1		T3	8		T13	5		T5	5
all_values[10]	374	1		T3	8		T13	5		T5	5
all_values[11]	374	1		T3	8		T13	5		T5	5
all_values[12]	374	1		T3	8		T13	5		T5	5
all_values[13]	374	1		T3	8		T13	5		T5	5
all_values[14]	374	1		T3	8		T13	5		T5	5
all_values[15]	374	1		T3	8		T13	5		T5	5
all_values[16]	374	1		T3	8		T13	5		T5	5
all_values[17]	374	1		T3	8		T13	5		T5	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3794	1		T3	84		T13	48		T5	46
auto[1]	2938	1		T3	60		T13	42		T5	44

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1628	1		T3	21		T13	21		T5	26
auto[1]	5104	1		T3	123		T13	69		T5	64

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	50	1		T19	2		T53	1		T54	1
all_values[0]	auto[0]	auto[1]	171	1		T3	5		T13	3		T5	4
all_values[0]	auto[1]	auto[0]	21	1		T3	1		T13	2		T14	1
all_values[0]	auto[1]	auto[1]	132	1		T3	2		T5	1		T12	6
all_values[1]	auto[0]	auto[0]	57	1		T15	1		T39	1		T19	2
all_values[1]	auto[0]	auto[1]	128	1		T3	1		T5	4		T12	3
all_values[1]	auto[1]	auto[0]	27	1		T13	5		T15	4		T35	1
all_values[1]	auto[1]	auto[1]	162	1		T3	7		T5	1		T12	5
all_values[2]	auto[0]	auto[0]	61	1		T14	2		T15	2		T35	1
all_values[2]	auto[0]	auto[1]	145	1		T3	5		T13	4		T5	3
all_values[2]	auto[1]	auto[0]	39	1		T3	1		T13	1		T5	2
all_values[2]	auto[1]	auto[1]	129	1		T3	2		T12	6		T35	3
all_values[3]	auto[0]	auto[0]	73	1		T15	3		T28	2		T37	2
all_values[3]	auto[0]	auto[1]	134	1		T3	8		T5	1		T12	2
all_values[3]	auto[1]	auto[0]	24	1		T14	1		T15	2		T38	1
all_values[3]	auto[1]	auto[1]	143	1		T13	5		T5	4		T12	6
all_values[4]	auto[0]	auto[0]	70	1		T13	3		T5	4		T14	2
all_values[4]	auto[0]	auto[1]	131	1		T3	7		T12	5		T28	2
all_values[4]	auto[1]	auto[0]	26	1		T3	1		T13	2		T5	1
all_values[4]	auto[1]	auto[1]	147	1		T12	3		T14	3		T15	4
all_values[5]	auto[0]	auto[0]	67	1		T3	1		T12	1		T28	1
all_values[5]	auto[0]	auto[1]	159	1		T3	3		T13	3		T5	3
all_values[5]	auto[1]	auto[0]	28	1		T13	1		T12	2		T14	1
all_values[5]	auto[1]	auto[1]	120	1		T3	4		T13	1		T5	2
all_values[6]	auto[0]	auto[0]	65	1		T15	4		T28	5		T39	1
all_values[6]	auto[0]	auto[1]	150	1		T3	3		T5	4		T12	7
all_values[6]	auto[1]	auto[0]	33	1		T3	1		T13	1		T5	1
all_values[6]	auto[1]	auto[1]	126	1		T3	4		T13	4		T12	1
all_values[7]	auto[0]	auto[0]	64	1		T13	1		T5	2		T12	1
all_values[7]	auto[0]	auto[1]	147	1		T3	5		T12	1		T14	1
all_values[7]	auto[1]	auto[0]	28	1		T3	1		T15	1		T28	1
all_values[7]	auto[1]	auto[1]	135	1		T3	2		T13	4		T5	3
all_values[8]	auto[0]	auto[0]	62	1		T14	1		T28	1		T19	2
all_values[8]	auto[0]	auto[1]	148	1		T3	7		T13	4		T5	3
all_values[8]	auto[1]	auto[0]	18	1		T13	1		T12	1		T35	2
all_values[8]	auto[1]	auto[1]	146	1		T3	1		T5	2		T12	6
all_values[9]	auto[0]	auto[0]	66	1		T14	1		T35	1		T37	4
all_values[9]	auto[0]	auto[1]	158	1		T3	5		T5	1		T12	1
all_values[9]	auto[1]	auto[0]	22	1		T13	1		T12	1		T14	1
all_values[9]	auto[1]	auto[1]	128	1		T3	3		T13	4		T5	4
all_values[10]	auto[0]	auto[0]	69	1		T3	2		T12	1		T37	1
all_values[10]	auto[0]	auto[1]	141	1		T3	3		T13	4		T12	5
all_values[10]	auto[1]	auto[0]	33	1		T3	1		T13	1		T5	1
all_values[10]	auto[1]	auto[1]	131	1		T3	2		T5	4		T12	2
all_values[11]	auto[0]	auto[0]	57	1		T3	1		T5	1		T36	1
all_values[11]	auto[0]	auto[1]	156	1		T3	4		T13	4		T12	2
all_values[11]	auto[1]	auto[0]	15	1		T14	1		T28	1		T38	2
all_values[11]	auto[1]	auto[1]	146	1		T3	3		T13	1		T5	4
all_values[12]	auto[0]	auto[0]	70	1		T5	2		T15	1		T36	6
all_values[12]	auto[0]	auto[1]	129	1		T3	7		T12	2		T14	3
all_values[12]	auto[1]	auto[0]	46	1		T13	1		T5	3		T12	1
all_values[12]	auto[1]	auto[1]	129	1		T3	1		T13	4		T12	5
all_values[13]	auto[0]	auto[0]	64	1		T3	2		T14	1		T15	1
all_values[13]	auto[0]	auto[1]	176	1		T3	4		T13	5		T5	4
all_values[13]	auto[1]	auto[0]	12	1		T3	2		T36	1		T39	1
all_values[13]	auto[1]	auto[1]	122	1		T5	1		T12	3		T15	1
all_values[14]	auto[0]	auto[0]	63	1		T12	1		T39	2		T19	2
all_values[14]	auto[0]	auto[1]	155	1		T3	6		T13	4		T5	3
all_values[14]	auto[1]	auto[0]	23	1		T14	5		T15	1		T35	1
all_values[14]	auto[1]	auto[1]	133	1		T3	2		T13	1		T5	2
all_values[15]	auto[0]	auto[0]	56	1		T5	2		T36	2		T38	1
all_values[15]	auto[0]	auto[1]	146	1		T3	1		T13	4		T12	3
all_values[15]	auto[1]	auto[0]	22	1		T3	1		T36	2		T38	1
all_values[15]	auto[1]	auto[1]	150	1		T3	6		T13	1		T5	3
all_values[16]	auto[0]	auto[0]	73	1		T3	2		T13	1		T14	1
all_values[16]	auto[0]	auto[1]	137	1		T3	1		T13	4		T12	1
all_values[16]	auto[1]	auto[0]	30	1		T3	2		T5	5		T12	1
all_values[16]	auto[1]	auto[1]	134	1		T3	3		T12	6		T14	3
all_values[17]	auto[0]	auto[0]	57	1		T3	1		T5	2		T15	1
all_values[17]	auto[0]	auto[1]	139	1		T13	4		T5	3		T12	3
all_values[17]	auto[1]	auto[0]	37	1		T3	1		T14	1		T28	5
all_values[17]	auto[1]	auto[1]	141	1		T3	6		T13	1		T12	5