Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
67.77	65.51	59.58	85.50	0.00	69.84	97.77	96.22

Total tests in report: 175

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
54.44	54.44	62.19	62.19	49.22	49.22	79.34	79.34	0.00	0.00	63.17	63.17	93.85	93.85	33.33	33.33	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.285678925
62.14	7.69	62.89	0.70	50.59	1.37	88.97	9.62	0.00	0.00	63.33	0.16	93.85	0.00	75.32	41.98	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.609181292
64.47	2.34	64.96	2.06	56.41	5.82	89.20	0.23	0.00	0.00	69.15	5.82	96.09	2.23	75.50	0.18	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2953198298
66.02	1.55	64.96	0.00	56.50	0.09	89.67	0.47	0.00	0.00	69.15	0.00	96.09	0.00	85.77	10.27	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.2782631320
67.30	1.28	65.22	0.26	58.79	2.28	90.38	0.70	0.00	0.00	69.23	0.08	97.21	1.12	90.27	4.50	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2647481074
67.75	0.46	65.22	0.00	58.79	0.00	92.49	2.11	0.00	0.00	69.23	0.00	97.21	0.00	91.35	1.08	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1939674634
68.14	0.39	65.22	0.00	58.79	0.00	92.49	0.00	0.00	0.00	69.23	0.00	97.21	0.00	94.05	2.70	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.4092874942
68.52	0.38	65.32	0.09	59.32	0.54	93.90	1.41	0.00	0.00	69.84	0.61	97.21	0.00	94.05	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3748278787
68.75	0.23	65.32	0.00	59.39	0.07	93.90	0.00	0.00	0.00	69.84	0.00	97.49	0.28	95.32	1.26	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.1565700477
68.84	0.09	65.32	0.00	59.51	0.12	94.13	0.23	0.00	0.00	69.84	0.00	97.77	0.28	95.32	0.00	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2260015373
68.89	0.05	65.32	0.00	59.51	0.00	94.13	0.00	0.00	0.00	69.84	0.00	97.77	0.00	95.68	0.36	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.932186013
68.94	0.05	65.32	0.00	59.51	0.00	94.13	0.00	0.00	0.00	69.84	0.00	97.77	0.00	96.04	0.36	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2828029532
68.98	0.04	65.51	0.19	59.58	0.07	94.13	0.00	0.00	0.00	69.84	0.00	97.77	0.00	96.04	0.00	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.513285469
69.01	0.03	65.51	0.00	59.58	0.00	94.13	0.00	0.00	0.00	69.84	0.00	97.77	0.00	96.22	0.18	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3443980717

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2967398875
/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.657274018
/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.587265016
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1189364457
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.44991819
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.405257900
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3766574199
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.567125157
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3835846774
/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.770044773
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.125320097
/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3062162415
/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4237193896
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.657118617
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.201880801
/workspace/coverage/cover_reg_top/1.usbdev_intr_test.931858699
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1177357736
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2989474557
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3480529572
/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2967515810
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1931379926
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.344011312
/workspace/coverage/cover_reg_top/10.usbdev_intr_test.1317325840
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.42349475
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.6838986
/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1471625430
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2183937132
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1138590048
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1322092090
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.588150701
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4225493540
/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1350300420
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3805691972
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.719117725
/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4202310358
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2316740893
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2998993092
/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3839700630
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.928196309
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4175470885
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3696504857
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.862273235
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.762206953
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3564640259
/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2800420155
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.887795920
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.465380924
/workspace/coverage/cover_reg_top/15.usbdev_intr_test.1119260255
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.19387841
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2717161543
/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.21940791
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2862352536
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.4133093216
/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1078961707
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3610332061
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3907148190
/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.581971144
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3244256771
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2415552916
/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2149997408
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1545294537
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.360093724
/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3831952823
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1940681776
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3583006937
/workspace/coverage/cover_reg_top/18.usbdev_intr_test.34966771
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2983872536
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2813904257
/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1608302655
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.833870913
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3569001440
/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3979421347
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2297480833
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1572507578
/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2900150277
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.82088546
/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1144498938
/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3580892951
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1800487474
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.463417658
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.3141346980
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.379932253
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3067539182
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.572438882
/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1846499846
/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3897060442
/workspace/coverage/cover_reg_top/20.usbdev_intr_test.162006595
/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4213297540
/workspace/coverage/cover_reg_top/22.usbdev_intr_test.2664085477
/workspace/coverage/cover_reg_top/23.usbdev_intr_test.3654400186
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.2651076660
/workspace/coverage/cover_reg_top/25.usbdev_intr_test.4221380458
/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2891923567
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.2455608018
/workspace/coverage/cover_reg_top/29.usbdev_intr_test.1117712710
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1622306522
/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4052886489
/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3279654807
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.758347704
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3718935760
/workspace/coverage/cover_reg_top/3.usbdev_intr_test.2887472502
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3666760228
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.239931004
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4291996625
/workspace/coverage/cover_reg_top/30.usbdev_intr_test.4175343923
/workspace/coverage/cover_reg_top/31.usbdev_intr_test.1537710058
/workspace/coverage/cover_reg_top/32.usbdev_intr_test.637185541
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.963141365
/workspace/coverage/cover_reg_top/34.usbdev_intr_test.2241129065
/workspace/coverage/cover_reg_top/35.usbdev_intr_test.448234377
/workspace/coverage/cover_reg_top/36.usbdev_intr_test.128732157
/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2071393131
/workspace/coverage/cover_reg_top/38.usbdev_intr_test.993190581
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3351066205
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3598189184
/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3394574423
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3964683331
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2349457856
/workspace/coverage/cover_reg_top/4.usbdev_intr_test.1959374241
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2299099960
/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1773804982
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4059776174
/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3390299701
/workspace/coverage/cover_reg_top/40.usbdev_intr_test.409954018
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.2654332410
/workspace/coverage/cover_reg_top/44.usbdev_intr_test.3626516107
/workspace/coverage/cover_reg_top/45.usbdev_intr_test.4106122161
/workspace/coverage/cover_reg_top/46.usbdev_intr_test.190206188
/workspace/coverage/cover_reg_top/47.usbdev_intr_test.2216326237
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.3287691723
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.197747200
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.760966719
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1445707641
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.673438229
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1131093155
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3893408171
/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2879088906
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.319563443
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.591083082
/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1327946041
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4065516396
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1446671835
/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2032589987
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1838467253
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3918758228
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.2167961891
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1753181411
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.307803620
/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1193885415
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3115356495
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.48601203
/workspace/coverage/cover_reg_top/8.usbdev_intr_test.2343305636
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.551516406
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2503237789
/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1062797705
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2409463671
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3391843890
/workspace/coverage/cover_reg_top/9.usbdev_intr_test.3997508187
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.416140848
/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2385313477
/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1254580752

Total test records in report: 175

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2316740893	Jul 19 04:37:10 PM PDT 24	Jul 19 04:37:29 PM PDT 24	121635863 ps
T2	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.887795920	Jul 19 04:37:10 PM PDT 24	Jul 19 04:37:28 PM PDT 24	146287661 ps
T3	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2891923567	Jul 19 04:37:22 PM PDT 24	Jul 19 04:37:33 PM PDT 24	43242285 ps
T6	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.19387841	Jul 19 04:37:19 PM PDT 24	Jul 19 04:37:32 PM PDT 24	180082503 ps
T13	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.3654400186	Jul 19 04:37:25 PM PDT 24	Jul 19 04:37:35 PM PDT 24	38378288 ps
T4	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.416140848	Jul 19 04:37:01 PM PDT 24	Jul 19 04:37:20 PM PDT 24	209985096 ps
T5	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3839700630	Jul 19 04:37:02 PM PDT 24	Jul 19 04:37:20 PM PDT 24	48181201 ps
T12	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.1565700477	Jul 19 04:37:19 PM PDT 24	Jul 19 04:37:31 PM PDT 24	42022828 ps
T7	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.285678925	Jul 19 04:36:43 PM PDT 24	Jul 19 04:37:15 PM PDT 24	972304729 ps
T16	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.581971144	Jul 19 04:37:19 PM PDT 24	Jul 19 04:37:33 PM PDT 24	512430679 ps
T14	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4213297540	Jul 19 04:37:21 PM PDT 24	Jul 19 04:37:32 PM PDT 24	48034395 ps
T15	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.993190581	Jul 19 04:37:23 PM PDT 24	Jul 19 04:37:34 PM PDT 24	59753059 ps
T28	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1327946041	Jul 19 04:37:07 PM PDT 24	Jul 19 04:37:24 PM PDT 24	35388883 ps
T29	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2998993092	Jul 19 04:37:09 PM PDT 24	Jul 19 04:37:26 PM PDT 24	138680586 ps
T30	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3391843890	Jul 19 04:36:58 PM PDT 24	Jul 19 04:37:19 PM PDT 24	85815890 ps
T31	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4225493540	Jul 19 04:37:04 PM PDT 24	Jul 19 04:37:22 PM PDT 24	48586175 ps
T35	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.2654332410	Jul 19 04:37:20 PM PDT 24	Jul 19 04:37:32 PM PDT 24	39971580 ps
T36	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.609181292	Jul 19 04:37:21 PM PDT 24	Jul 19 04:37:32 PM PDT 24	73196475 ps
T37	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.2343305636	Jul 19 04:36:58 PM PDT 24	Jul 19 04:37:18 PM PDT 24	34778610 ps
T17	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1931379926	Jul 19 04:36:59 PM PDT 24	Jul 19 04:37:20 PM PDT 24	161437004 ps
T18	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.833870913	Jul 19 04:37:18 PM PDT 24	Jul 19 04:37:31 PM PDT 24	92604370 ps
T38	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.4092874942	Jul 19 04:37:20 PM PDT 24	Jul 19 04:37:31 PM PDT 24	39063616 ps
T39	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.2782631320	Jul 19 04:37:25 PM PDT 24	Jul 19 04:37:35 PM PDT 24	39641695 ps
T19	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2647481074	Jul 19 04:36:45 PM PDT 24	Jul 19 04:37:15 PM PDT 24	309216036 ps
T20	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3244256771	Jul 19 04:37:10 PM PDT 24	Jul 19 04:37:28 PM PDT 24	125958239 ps
T55	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1078961707	Jul 19 04:37:11 PM PDT 24	Jul 19 04:37:27 PM PDT 24	72153904 ps
T67	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.44991819	Jul 19 04:36:35 PM PDT 24	Jul 19 04:37:09 PM PDT 24	85861009 ps
T45	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1545294537	Jul 19 04:37:11 PM PDT 24	Jul 19 04:37:28 PM PDT 24	109755176 ps
T53	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.4106122161	Jul 19 04:37:23 PM PDT 24	Jul 19 04:37:34 PM PDT 24	66748938 ps
T68	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1350300420	Jul 19 04:37:03 PM PDT 24	Jul 19 04:37:21 PM PDT 24	32890091 ps
T32	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2260015373	Jul 19 04:37:06 PM PDT 24	Jul 19 04:37:23 PM PDT 24	82143850 ps
T25	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4202310358	Jul 19 04:37:06 PM PDT 24	Jul 19 04:37:26 PM PDT 24	681367634 ps
T54	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.3626516107	Jul 19 04:37:26 PM PDT 24	Jul 19 04:37:35 PM PDT 24	63233500 ps
T47	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4052886489	Jul 19 04:36:44 PM PDT 24	Jul 19 04:37:17 PM PDT 24	1019289521 ps
T21	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.719117725	Jul 19 04:37:02 PM PDT 24	Jul 19 04:37:21 PM PDT 24	64175721 ps
T22	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3893408171	Jul 19 04:36:53 PM PDT 24	Jul 19 04:37:16 PM PDT 24	204678380 ps
T26	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3831952823	Jul 19 04:37:16 PM PDT 24	Jul 19 04:37:32 PM PDT 24	452406421 ps
T11	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2953198298	Jul 19 04:36:55 PM PDT 24	Jul 19 04:37:17 PM PDT 24	88286139 ps
T23	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.758347704	Jul 19 04:36:55 PM PDT 24	Jul 19 04:37:19 PM PDT 24	184849688 ps
T33	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.42349475	Jul 19 04:37:00 PM PDT 24	Jul 19 04:37:20 PM PDT 24	348078342 ps
T61	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.770044773	Jul 19 04:36:33 PM PDT 24	Jul 19 04:37:14 PM PDT 24	1953751142 ps
T46	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.928196309	Jul 19 04:37:09 PM PDT 24	Jul 19 04:37:27 PM PDT 24	161785030 ps
T24	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.379932253	Jul 19 04:36:37 PM PDT 24	Jul 19 04:37:12 PM PDT 24	253505789 ps
T8	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3580892951	Jul 19 04:36:41 PM PDT 24	Jul 19 04:37:12 PM PDT 24	51736583 ps
T27	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2828029532	Jul 19 04:37:03 PM PDT 24	Jul 19 04:37:26 PM PDT 24	1433750078 ps
T34	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1622306522	Jul 19 04:36:42 PM PDT 24	Jul 19 04:37:15 PM PDT 24	366030349 ps
T69	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.657274018	Jul 19 04:36:27 PM PDT 24	Jul 19 04:37:08 PM PDT 24	737318085 ps
T70	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.409954018	Jul 19 04:37:22 PM PDT 24	Jul 19 04:37:33 PM PDT 24	35559334 ps
T40	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.344011312	Jul 19 04:37:02 PM PDT 24	Jul 19 04:37:20 PM PDT 24	78752283 ps
T56	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1939674634	Jul 19 04:37:00 PM PDT 24	Jul 19 04:37:23 PM PDT 24	766453882 ps
T41	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.463417658	Jul 19 04:36:36 PM PDT 24	Jul 19 04:37:10 PM PDT 24	50152143 ps
T71	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.551516406	Jul 19 04:36:54 PM PDT 24	Jul 19 04:37:17 PM PDT 24	150916404 ps
T72	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3964683331	Jul 19 04:36:57 PM PDT 24	Jul 19 04:37:19 PM PDT 24	139039115 ps
T73	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.2216326237	Jul 19 04:37:23 PM PDT 24	Jul 19 04:37:34 PM PDT 24	62323837 ps
T74	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3979421347	Jul 19 04:37:17 PM PDT 24	Jul 19 04:37:30 PM PDT 24	58798399 ps
T75	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.2455608018	Jul 19 04:37:23 PM PDT 24	Jul 19 04:37:34 PM PDT 24	66944018 ps
T49	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2967515810	Jul 19 04:36:44 PM PDT 24	Jul 19 04:37:14 PM PDT 24	111032018 ps
T57	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2800420155	Jul 19 04:37:11 PM PDT 24	Jul 19 04:37:32 PM PDT 24	1641464632 ps
T42	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3569001440	Jul 19 04:37:19 PM PDT 24	Jul 19 04:37:31 PM PDT 24	46263454 ps
T76	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2071393131	Jul 19 04:37:22 PM PDT 24	Jul 19 04:37:33 PM PDT 24	57006061 ps
T62	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1193885415	Jul 19 04:36:55 PM PDT 24	Jul 19 04:37:21 PM PDT 24	803733622 ps
T77	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1131093155	Jul 19 04:36:55 PM PDT 24	Jul 19 04:37:19 PM PDT 24	400485538 ps
T78	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3766574199	Jul 19 04:36:40 PM PDT 24	Jul 19 04:37:15 PM PDT 24	755411674 ps
T79	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2862352536	Jul 19 04:37:11 PM PDT 24	Jul 19 04:37:28 PM PDT 24	150492697 ps
T80	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.4221380458	Jul 19 04:37:25 PM PDT 24	Jul 19 04:37:35 PM PDT 24	42064504 ps
T59	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1471625430	Jul 19 04:36:59 PM PDT 24	Jul 19 04:37:24 PM PDT 24	1298270992 ps
T43	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2299099960	Jul 19 04:36:55 PM PDT 24	Jul 19 04:37:19 PM PDT 24	124497100 ps
T81	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.4133093216	Jul 19 04:37:16 PM PDT 24	Jul 19 04:37:30 PM PDT 24	87094602 ps
T82	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2183937132	Jul 19 04:37:03 PM PDT 24	Jul 19 04:37:22 PM PDT 24	112014669 ps
T83	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.448234377	Jul 19 04:37:20 PM PDT 24	Jul 19 04:37:32 PM PDT 24	39178564 ps
T63	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2879088906	Jul 19 04:36:55 PM PDT 24	Jul 19 04:37:21 PM PDT 24	691982298 ps
T52	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.657118617	Jul 19 04:36:42 PM PDT 24	Jul 19 04:37:13 PM PDT 24	123196066 ps
T44	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2415552916	Jul 19 04:37:12 PM PDT 24	Jul 19 04:37:28 PM PDT 24	82879021 ps
T84	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.3997508187	Jul 19 04:37:04 PM PDT 24	Jul 19 04:37:21 PM PDT 24	38923671 ps
T50	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.513285469	Jul 19 04:36:43 PM PDT 24	Jul 19 04:37:15 PM PDT 24	292983021 ps
T85	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.2651076660	Jul 19 04:37:21 PM PDT 24	Jul 19 04:37:33 PM PDT 24	54881236 ps
T86	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.637185541	Jul 19 04:37:21 PM PDT 24	Jul 19 04:37:32 PM PDT 24	34033499 ps
T48	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4237193896	Jul 19 04:36:38 PM PDT 24	Jul 19 04:37:11 PM PDT 24	64692986 ps
T51	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1846499846	Jul 19 04:36:40 PM PDT 24	Jul 19 04:37:13 PM PDT 24	282437141 ps
T87	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2409463671	Jul 19 04:36:59 PM PDT 24	Jul 19 04:37:21 PM PDT 24	162405419 ps
T88	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.405257900	Jul 19 04:36:35 PM PDT 24	Jul 19 04:37:11 PM PDT 24	73899896 ps
T89	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.1959374241	Jul 19 04:36:54 PM PDT 24	Jul 19 04:37:17 PM PDT 24	35345725 ps
T90	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1445707641	Jul 19 04:36:54 PM PDT 24	Jul 19 04:37:17 PM PDT 24	45314908 ps
T91	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.932186013	Jul 19 04:37:02 PM PDT 24	Jul 19 04:37:20 PM PDT 24	78622077 ps
T92	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2149997408	Jul 19 04:37:12 PM PDT 24	Jul 19 04:37:28 PM PDT 24	55478552 ps
T93	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.162006595	Jul 19 04:37:22 PM PDT 24	Jul 19 04:37:33 PM PDT 24	55589975 ps
T94	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3062162415	Jul 19 04:36:55 PM PDT 24	Jul 19 04:37:24 PM PDT 24	470701514 ps
T95	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.3141346980	Jul 19 04:36:40 PM PDT 24	Jul 19 04:37:11 PM PDT 24	36010739 ps
T96	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.319563443	Jul 19 04:36:52 PM PDT 24	Jul 19 04:37:16 PM PDT 24	210169384 ps
T97	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1800487474	Jul 19 04:36:34 PM PDT 24	Jul 19 04:37:10 PM PDT 24	249404284 ps
T64	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2032589987	Jul 19 04:36:56 PM PDT 24	Jul 19 04:37:19 PM PDT 24	333583902 ps
T98	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3805691972	Jul 19 04:37:04 PM PDT 24	Jul 19 04:37:22 PM PDT 24	205749126 ps
T99	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1177357736	Jul 19 04:36:44 PM PDT 24	Jul 19 04:37:14 PM PDT 24	83949406 ps
T100	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.201880801	Jul 19 04:36:41 PM PDT 24	Jul 19 04:37:12 PM PDT 24	57187904 ps
T101	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.760966719	Jul 19 04:36:56 PM PDT 24	Jul 19 04:37:20 PM PDT 24	100562380 ps
T102	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.862273235	Jul 19 04:37:17 PM PDT 24	Jul 19 04:37:31 PM PDT 24	76983964 ps
T103	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1138590048	Jul 19 04:37:02 PM PDT 24	Jul 19 04:37:20 PM PDT 24	113275212 ps
T104	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.1117712710	Jul 19 04:37:24 PM PDT 24	Jul 19 04:37:35 PM PDT 24	30972025 ps
T105	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1773804982	Jul 19 04:36:53 PM PDT 24	Jul 19 04:37:18 PM PDT 24	371641747 ps
T106	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1838467253	Jul 19 04:36:54 PM PDT 24	Jul 19 04:37:18 PM PDT 24	205278267 ps
T107	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.197747200	Jul 19 04:37:20 PM PDT 24	Jul 19 04:37:32 PM PDT 24	39666699 ps
T108	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1322092090	Jul 19 04:37:02 PM PDT 24	Jul 19 04:37:22 PM PDT 24	232337334 ps
T109	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3115356495	Jul 19 04:37:01 PM PDT 24	Jul 19 04:37:20 PM PDT 24	198778377 ps
T110	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4291996625	Jul 19 04:36:45 PM PDT 24	Jul 19 04:37:14 PM PDT 24	87242173 ps
T111	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1062797705	Jul 19 04:36:58 PM PDT 24	Jul 19 04:37:20 PM PDT 24	350791239 ps
T112	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4175470885	Jul 19 04:37:02 PM PDT 24	Jul 19 04:37:21 PM PDT 24	147193466 ps
T9	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3748278787	Jul 19 04:36:40 PM PDT 24	Jul 19 04:37:11 PM PDT 24	71275476 ps
T58	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3897060442	Jul 19 04:36:37 PM PDT 24	Jul 19 04:37:15 PM PDT 24	1613250226 ps
T113	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.587265016	Jul 19 04:36:36 PM PDT 24	Jul 19 04:37:11 PM PDT 24	194292605 ps
T60	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.21940791	Jul 19 04:37:11 PM PDT 24	Jul 19 04:37:31 PM PDT 24	742115740 ps
T114	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3696504857	Jul 19 04:37:19 PM PDT 24	Jul 19 04:37:32 PM PDT 24	155055024 ps
T115	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4065516396	Jul 19 04:36:54 PM PDT 24	Jul 19 04:37:18 PM PDT 24	107590680 ps
T116	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3598189184	Jul 19 04:36:52 PM PDT 24	Jul 19 04:37:17 PM PDT 24	125317535 ps
T117	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2503237789	Jul 19 04:36:57 PM PDT 24	Jul 19 04:37:20 PM PDT 24	262681532 ps
T118	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3583006937	Jul 19 04:37:12 PM PDT 24	Jul 19 04:37:28 PM PDT 24	110922149 ps
T119	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.34966771	Jul 19 04:37:22 PM PDT 24	Jul 19 04:37:33 PM PDT 24	39638941 ps
T120	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.190206188	Jul 19 04:37:22 PM PDT 24	Jul 19 04:37:33 PM PDT 24	40639368 ps
T121	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.2664085477	Jul 19 04:37:19 PM PDT 24	Jul 19 04:37:31 PM PDT 24	52536993 ps
T122	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3718935760	Jul 19 04:36:41 PM PDT 24	Jul 19 04:37:12 PM PDT 24	71289378 ps
T123	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3907148190	Jul 19 04:37:12 PM PDT 24	Jul 19 04:37:29 PM PDT 24	87221886 ps
T124	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.360093724	Jul 19 04:37:22 PM PDT 24	Jul 19 04:37:35 PM PDT 24	244814734 ps
T125	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.128732157	Jul 19 04:37:21 PM PDT 24	Jul 19 04:37:32 PM PDT 24	33778287 ps
T126	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.4175343923	Jul 19 04:37:23 PM PDT 24	Jul 19 04:37:33 PM PDT 24	42209995 ps
T127	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2813904257	Jul 19 04:37:19 PM PDT 24	Jul 19 04:37:33 PM PDT 24	101987200 ps
T128	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.931858699	Jul 19 04:36:38 PM PDT 24	Jul 19 04:37:10 PM PDT 24	75767523 ps
T129	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3564640259	Jul 19 04:37:16 PM PDT 24	Jul 19 04:37:31 PM PDT 24	237942419 ps
T130	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.963141365	Jul 19 04:37:21 PM PDT 24	Jul 19 04:37:32 PM PDT 24	42679778 ps
T131	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1446671835	Jul 19 04:36:56 PM PDT 24	Jul 19 04:37:19 PM PDT 24	142122912 ps
T132	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1940681776	Jul 19 04:37:19 PM PDT 24	Jul 19 04:37:32 PM PDT 24	91597944 ps
T133	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.82088546	Jul 19 04:36:42 PM PDT 24	Jul 19 04:37:13 PM PDT 24	203372953 ps
T134	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.1119260255	Jul 19 04:37:19 PM PDT 24	Jul 19 04:37:31 PM PDT 24	50075903 ps
T135	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2297480833	Jul 19 04:37:25 PM PDT 24	Jul 19 04:37:35 PM PDT 24	105121874 ps
T136	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.125320097	Jul 19 04:36:43 PM PDT 24	Jul 19 04:37:14 PM PDT 24	230997360 ps
T137	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3351066205	Jul 19 04:37:23 PM PDT 24	Jul 19 04:37:34 PM PDT 24	69178031 ps
T10	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3279654807	Jul 19 04:36:47 PM PDT 24	Jul 19 04:37:13 PM PDT 24	62789545 ps
T138	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2385313477	Jul 19 04:37:03 PM PDT 24	Jul 19 04:37:22 PM PDT 24	74050208 ps
T139	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2967398875	Jul 19 04:36:35 PM PDT 24	Jul 19 04:37:12 PM PDT 24	120555381 ps
T140	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2989474557	Jul 19 04:36:46 PM PDT 24	Jul 19 04:37:17 PM PDT 24	733595124 ps
T141	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2349457856	Jul 19 04:36:51 PM PDT 24	Jul 19 04:37:14 PM PDT 24	116450354 ps
T142	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2900150277	Jul 19 04:37:09 PM PDT 24	Jul 19 04:37:28 PM PDT 24	279292781 ps
T143	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.1317325840	Jul 19 04:37:00 PM PDT 24	Jul 19 04:37:19 PM PDT 24	35424033 ps
T144	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1189364457	Jul 19 04:36:29 PM PDT 24	Jul 19 04:37:06 PM PDT 24	49830701 ps
T145	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.591083082	Jul 19 04:36:52 PM PDT 24	Jul 19 04:37:15 PM PDT 24	94875604 ps
T146	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3443980717	Jul 19 04:36:45 PM PDT 24	Jul 19 04:37:17 PM PDT 24	792662086 ps
T147	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.2887472502	Jul 19 04:36:45 PM PDT 24	Jul 19 04:37:13 PM PDT 24	50972086 ps
T148	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.2241129065	Jul 19 04:37:21 PM PDT 24	Jul 19 04:37:32 PM PDT 24	43275047 ps
T149	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3390299701	Jul 19 04:36:46 PM PDT 24	Jul 19 04:37:18 PM PDT 24	1696969722 ps
T150	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3610332061	Jul 19 04:37:11 PM PDT 24	Jul 19 04:37:28 PM PDT 24	108818079 ps
T151	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.567125157	Jul 19 04:36:27 PM PDT 24	Jul 19 04:37:05 PM PDT 24	336402173 ps
T152	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.307803620	Jul 19 04:36:55 PM PDT 24	Jul 19 04:37:18 PM PDT 24	175134057 ps
T153	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.48601203	Jul 19 04:37:01 PM PDT 24	Jul 19 04:37:20 PM PDT 24	86840241 ps
T154	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2983872536	Jul 19 04:37:19 PM PDT 24	Jul 19 04:37:32 PM PDT 24	305753764 ps
T155	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1572507578	Jul 19 04:37:13 PM PDT 24	Jul 19 04:37:30 PM PDT 24	221646204 ps
T156	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.588150701	Jul 19 04:37:03 PM PDT 24	Jul 19 04:37:22 PM PDT 24	207044252 ps
T157	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.2167961891	Jul 19 04:36:57 PM PDT 24	Jul 19 04:37:18 PM PDT 24	70161265 ps
T158	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.239931004	Jul 19 04:36:44 PM PDT 24	Jul 19 04:37:15 PM PDT 24	371643093 ps
T159	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1753181411	Jul 19 04:37:07 PM PDT 24	Jul 19 04:37:25 PM PDT 24	464240126 ps
T160	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1144498938	Jul 19 04:36:55 PM PDT 24	Jul 19 04:37:26 PM PDT 24	1735284879 ps
T161	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.762206953	Jul 19 04:37:21 PM PDT 24	Jul 19 04:37:33 PM PDT 24	161303145 ps
T162	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.6838986	Jul 19 04:37:00 PM PDT 24	Jul 19 04:37:20 PM PDT 24	143348190 ps
T163	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3394574423	Jul 19 04:36:53 PM PDT 24	Jul 19 04:37:21 PM PDT 24	893315342 ps
T164	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3835846774	Jul 19 04:36:40 PM PDT 24	Jul 19 04:37:14 PM PDT 24	365148489 ps
T165	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.572438882	Jul 19 04:36:48 PM PDT 24	Jul 19 04:37:14 PM PDT 24	227085924 ps
T166	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3666760228	Jul 19 04:36:44 PM PDT 24	Jul 19 04:37:13 PM PDT 24	111876439 ps
T167	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.673438229	Jul 19 04:36:55 PM PDT 24	Jul 19 04:37:17 PM PDT 24	76751061 ps
T168	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3067539182	Jul 19 04:36:46 PM PDT 24	Jul 19 04:37:15 PM PDT 24	250649103 ps
T65	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1254580752	Jul 19 04:37:04 PM PDT 24	Jul 19 04:37:23 PM PDT 24	436959656 ps
T169	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.1537710058	Jul 19 04:37:20 PM PDT 24	Jul 19 04:37:32 PM PDT 24	93259941 ps
T170	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2717161543	Jul 19 04:37:11 PM PDT 24	Jul 19 04:37:28 PM PDT 24	141609480 ps
T171	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3918758228	Jul 19 04:37:07 PM PDT 24	Jul 19 04:37:24 PM PDT 24	52603891 ps
T172	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4059776174	Jul 19 04:36:51 PM PDT 24	Jul 19 04:37:15 PM PDT 24	243462424 ps
T173	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.465380924	Jul 19 04:37:12 PM PDT 24	Jul 19 04:37:28 PM PDT 24	63882410 ps
T66	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1608302655	Jul 19 04:37:11 PM PDT 24	Jul 19 04:37:29 PM PDT 24	934154932 ps
T174	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3480529572	Jul 19 04:36:44 PM PDT 24	Jul 19 04:37:13 PM PDT 24	179541885 ps
T175	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.3287691723	Jul 19 04:37:24 PM PDT 24	Jul 19 04:37:35 PM PDT 24	41273210 ps

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.285678925
Short name	T7
Test name
Test status
Simulation time	972304729 ps
CPU time	3.15 seconds
Started	Jul 19 04:36:43 PM PDT 24
Finished	Jul 19 04:37:15 PM PDT 24
Peak memory	206404 kb
Host	smart-a2e88706-ef22-43d7-bf68-bb8faa2aeb5e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=285678925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.285678925
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.609181292
Short name	T36
Test name
Test status
Simulation time	73196475 ps
CPU time	0.71 seconds
Started	Jul 19 04:37:21 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206204 kb
Host	smart-901f9902-41b0-4c14-be61-2ad076593145
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=609181292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.609181292
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2953198298
Short name	T11
Test name
Test status
Simulation time	88286139 ps
CPU time	0.81 seconds
Started	Jul 19 04:36:55 PM PDT 24
Finished	Jul 19 04:37:17 PM PDT 24
Peak memory	206220 kb
Host	smart-4fe85c90-2e31-4dfe-bad6-e04dc7b3ab6b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2953198298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2953198298
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.2782631320
Short name	T39
Test name
Test status
Simulation time	39641695 ps
CPU time	0.68 seconds
Started	Jul 19 04:37:25 PM PDT 24
Finished	Jul 19 04:37:35 PM PDT 24
Peak memory	206180 kb
Host	smart-b50bc2ea-432d-4d6c-9e71-79b65b249d56
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2782631320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2782631320
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2647481074
Short name	T19
Test name
Test status
Simulation time	309216036 ps
CPU time	3.22 seconds
Started	Jul 19 04:36:45 PM PDT 24
Finished	Jul 19 04:37:15 PM PDT 24
Peak memory	222164 kb
Host	smart-70cc40a2-1f3b-4085-87bc-6a91efdb169b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2647481074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2647481074
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1939674634
Short name	T56
Test name
Test status
Simulation time	766453882 ps
CPU time	4.84 seconds
Started	Jul 19 04:37:00 PM PDT 24
Finished	Jul 19 04:37:23 PM PDT 24
Peak memory	206612 kb
Host	smart-4f4d6ebd-0ff1-43ca-a705-a7c44cea20bc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1939674634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1939674634
Directory	/workspace/11.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.4092874942
Short name	T38
Test name
Test status
Simulation time	39063616 ps
CPU time	0.69 seconds
Started	Jul 19 04:37:20 PM PDT 24
Finished	Jul 19 04:37:31 PM PDT 24
Peak memory	206200 kb
Host	smart-f7823e56-3d69-40af-bcd4-f0e0e1524b76
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4092874942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.4092874942
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3748278787
Short name	T9
Test name
Test status
Simulation time	71275476 ps
CPU time	0.91 seconds
Started	Jul 19 04:36:40 PM PDT 24
Finished	Jul 19 04:37:11 PM PDT 24
Peak memory	206068 kb
Host	smart-09728580-654a-4d10-9193-5eebca52548f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3748278787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3748278787
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.1565700477
Short name	T12
Test name
Test status
Simulation time	42022828 ps
CPU time	0.71 seconds
Started	Jul 19 04:37:19 PM PDT 24
Finished	Jul 19 04:37:31 PM PDT 24
Peak memory	206184 kb
Host	smart-5c588ef4-3d9a-4a26-af87-9fbcc49b4acb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1565700477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1565700477
Directory	/workspace/14.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2260015373
Short name	T32
Test name
Test status
Simulation time	82143850 ps
CPU time	0.99 seconds
Started	Jul 19 04:37:06 PM PDT 24
Finished	Jul 19 04:37:23 PM PDT 24
Peak memory	206352 kb
Host	smart-bbcbf656-9150-4729-97d3-0163825906a3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2260015373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2260015373
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.932186013
Short name	T91
Test name
Test status
Simulation time	78622077 ps
CPU time	0.76 seconds
Started	Jul 19 04:37:02 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	206200 kb
Host	smart-5652361e-34b1-4e6b-a81d-255f3191431e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=932186013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.932186013
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2828029532
Short name	T27
Test name
Test status
Simulation time	1433750078 ps
CPU time	5.14 seconds
Started	Jul 19 04:37:03 PM PDT 24
Finished	Jul 19 04:37:26 PM PDT 24
Peak memory	206428 kb
Host	smart-591484cb-a6f8-4aae-9f50-49ec4c7ecfcf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2828029532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2828029532
Directory	/workspace/13.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.513285469
Short name	T50
Test name
Test status
Simulation time	292983021 ps
CPU time	2.99 seconds
Started	Jul 19 04:36:43 PM PDT 24
Finished	Jul 19 04:37:15 PM PDT 24
Peak memory	222668 kb
Host	smart-eba5464a-4831-4873-a9e6-3387927fc0b8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=513285469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.513285469
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3443980717
Short name	T146
Test name
Test status
Simulation time	792662086 ps
CPU time	4.7 seconds
Started	Jul 19 04:36:45 PM PDT 24
Finished	Jul 19 04:37:17 PM PDT 24
Peak memory	206380 kb
Host	smart-3470ca4e-dcf7-4d12-a2f8-e36e45f47c9e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3443980717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3443980717
Directory	/workspace/1.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2967398875
Short name	T139
Test name
Test status
Simulation time	120555381 ps
CPU time	3.21 seconds
Started	Jul 19 04:36:35 PM PDT 24
Finished	Jul 19 04:37:12 PM PDT 24
Peak memory	206372 kb
Host	smart-37e775e8-833b-4577-a26f-3ab3e1a21d7d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2967398875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2967398875
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.657274018
Short name	T69
Test name
Test status
Simulation time	737318085 ps
CPU time	4.7 seconds
Started	Jul 19 04:36:27 PM PDT 24
Finished	Jul 19 04:37:08 PM PDT 24
Peak memory	206336 kb
Host	smart-20c374e9-3d70-4bc4-9f57-ff5cf42d21a4
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=657274018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.657274018
Directory	/workspace/0.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.587265016
Short name	T113
Test name
Test status
Simulation time	194292605 ps
CPU time	2.16 seconds
Started	Jul 19 04:36:36 PM PDT 24
Finished	Jul 19 04:37:11 PM PDT 24
Peak memory	222816 kb
Host	smart-269db560-0bc3-4a8e-a903-126e2c8bcc88
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587265016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev _csr_mem_rw_with_rand_reset.587265016
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1189364457
Short name	T144
Test name
Test status
Simulation time	49830701 ps
CPU time	0.98 seconds
Started	Jul 19 04:36:29 PM PDT 24
Finished	Jul 19 04:37:06 PM PDT 24
Peak memory	206316 kb
Host	smart-d0dc0cb5-4273-4ca9-b906-5c88c220d363
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1189364457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1189364457
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.44991819
Short name	T67
Test name
Test status
Simulation time	85861009 ps
CPU time	0.71 seconds
Started	Jul 19 04:36:35 PM PDT 24
Finished	Jul 19 04:37:09 PM PDT 24
Peak memory	206192 kb
Host	smart-e92ec54d-9d87-46b9-a471-288e38fc5918
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=44991819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.44991819
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.405257900
Short name	T88
Test name
Test status
Simulation time	73899896 ps
CPU time	2.12 seconds
Started	Jul 19 04:36:35 PM PDT 24
Finished	Jul 19 04:37:11 PM PDT 24
Peak memory	214644 kb
Host	smart-0843df4a-5e1d-4dc7-b5f8-eba46b42de34
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=405257900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.405257900
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3766574199
Short name	T78
Test name
Test status
Simulation time	755411674 ps
CPU time	4.63 seconds
Started	Jul 19 04:36:40 PM PDT 24
Finished	Jul 19 04:37:15 PM PDT 24
Peak memory	206284 kb
Host	smart-d3241bf6-98cf-438e-9ad1-d999784e7227
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3766574199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3766574199
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.567125157
Short name	T151
Test name
Test status
Simulation time	336402173 ps
CPU time	1.8 seconds
Started	Jul 19 04:36:27 PM PDT 24
Finished	Jul 19 04:37:05 PM PDT 24
Peak memory	206376 kb
Host	smart-99d7a865-b240-4e06-a837-f164f9ecc7e7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=567125157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.567125157
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.3835846774
Short name	T164
Test name
Test status
Simulation time	365148489 ps
CPU time	3.15 seconds
Started	Jul 19 04:36:40 PM PDT 24
Finished	Jul 19 04:37:14 PM PDT 24
Peak memory	222304 kb
Host	smart-3a594bb5-b20c-4d8d-b957-f420abef742a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3835846774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.3835846774
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.770044773
Short name	T61
Test name
Test status
Simulation time	1953751142 ps
CPU time	6.2 seconds
Started	Jul 19 04:36:33 PM PDT 24
Finished	Jul 19 04:37:14 PM PDT 24
Peak memory	206464 kb
Host	smart-04558a07-4e52-49f9-896a-e1d99faca56e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=770044773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.770044773
Directory	/workspace/0.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.125320097
Short name	T136
Test name
Test status
Simulation time	230997360 ps
CPU time	2.08 seconds
Started	Jul 19 04:36:43 PM PDT 24
Finished	Jul 19 04:37:14 PM PDT 24
Peak memory	206396 kb
Host	smart-7e46896a-04a5-4d74-a5a6-483f367f0684
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=125320097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.125320097
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3062162415
Short name	T94
Test name
Test status
Simulation time	470701514 ps
CPU time	7.59 seconds
Started	Jul 19 04:36:55 PM PDT 24
Finished	Jul 19 04:37:24 PM PDT 24
Peak memory	206308 kb
Host	smart-6eb337ca-7819-403c-8625-0ffb9c319c57
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3062162415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3062162415
Directory	/workspace/1.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.4237193896
Short name	T48
Test name
Test status
Simulation time	64692986 ps
CPU time	0.78 seconds
Started	Jul 19 04:36:38 PM PDT 24
Finished	Jul 19 04:37:11 PM PDT 24
Peak memory	206296 kb
Host	smart-61370595-bbb1-4e99-be6f-afba2325140f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4237193896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.4237193896
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.657118617
Short name	T52
Test name
Test status
Simulation time	123196066 ps
CPU time	1.28 seconds
Started	Jul 19 04:36:42 PM PDT 24
Finished	Jul 19 04:37:13 PM PDT 24
Peak memory	214660 kb
Host	smart-31caa61e-0d9e-49ce-bf7a-09ee45a5a45c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657118617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev _csr_mem_rw_with_rand_reset.657118617
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.201880801
Short name	T100
Test name
Test status
Simulation time	57187904 ps
CPU time	0.8 seconds
Started	Jul 19 04:36:41 PM PDT 24
Finished	Jul 19 04:37:12 PM PDT 24
Peak memory	206252 kb
Host	smart-ad1ad44a-c83d-47b2-b49a-67f02662e4c1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=201880801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.201880801
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.931858699
Short name	T128
Test name
Test status
Simulation time	75767523 ps
CPU time	0.77 seconds
Started	Jul 19 04:36:38 PM PDT 24
Finished	Jul 19 04:37:10 PM PDT 24
Peak memory	206172 kb
Host	smart-7ebd6377-f9be-44a6-97a5-4db8e4dbcbeb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=931858699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.931858699
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1177357736
Short name	T99
Test name
Test status
Simulation time	83949406 ps
CPU time	2.05 seconds
Started	Jul 19 04:36:44 PM PDT 24
Finished	Jul 19 04:37:14 PM PDT 24
Peak memory	214708 kb
Host	smart-ec30c787-bf17-41d2-9c82-b55ab19d2524
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1177357736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1177357736
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2989474557
Short name	T140
Test name
Test status
Simulation time	733595124 ps
CPU time	4.8 seconds
Started	Jul 19 04:36:46 PM PDT 24
Finished	Jul 19 04:37:17 PM PDT 24
Peak memory	206276 kb
Host	smart-80e0edcf-2fbf-4003-888a-52be520fa596
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2989474557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2989474557
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3480529572
Short name	T174
Test name
Test status
Simulation time	179541885 ps
CPU time	1.52 seconds
Started	Jul 19 04:36:44 PM PDT 24
Finished	Jul 19 04:37:13 PM PDT 24
Peak memory	206348 kb
Host	smart-e877ce48-477a-4dde-8433-45f720de3ae7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3480529572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.3480529572
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2967515810
Short name	T49
Test name
Test status
Simulation time	111032018 ps
CPU time	2.47 seconds
Started	Jul 19 04:36:44 PM PDT 24
Finished	Jul 19 04:37:14 PM PDT 24
Peak memory	215684 kb
Host	smart-46ea51c6-bf70-4508-a4c9-48e84e7d777c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2967515810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2967515810
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1931379926
Short name	T17
Test name
Test status
Simulation time	161437004 ps
CPU time	1.68 seconds
Started	Jul 19 04:36:59 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	218216 kb
Host	smart-ecd76e25-31ee-4677-bc03-7b0689a8b660
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931379926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd ev_csr_mem_rw_with_rand_reset.1931379926
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.344011312
Short name	T40
Test name
Test status
Simulation time	78752283 ps
CPU time	1.05 seconds
Started	Jul 19 04:37:02 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	206372 kb
Host	smart-7950bdf6-9a8c-480a-bd62-1678c67edd44
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=344011312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.344011312
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.1317325840
Short name	T143
Test name
Test status
Simulation time	35424033 ps
CPU time	0.64 seconds
Started	Jul 19 04:37:00 PM PDT 24
Finished	Jul 19 04:37:19 PM PDT 24
Peak memory	206320 kb
Host	smart-7994b6ad-55b8-4dac-9e67-6e8607322fb4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1317325840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1317325840
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.42349475
Short name	T33
Test name
Test status
Simulation time	348078342 ps
CPU time	1.81 seconds
Started	Jul 19 04:37:00 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	206448 kb
Host	smart-35804411-2d6b-43bb-bbb1-4ebd1af78c5c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=42349475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.42349475
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.6838986
Short name	T162
Test name
Test status
Simulation time	143348190 ps
CPU time	1.75 seconds
Started	Jul 19 04:37:00 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	214680 kb
Host	smart-6c2e8c9a-e955-4e6b-8886-440095207142
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=6838986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.6838986
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1471625430
Short name	T59
Test name
Test status
Simulation time	1298270992 ps
CPU time	5.28 seconds
Started	Jul 19 04:36:59 PM PDT 24
Finished	Jul 19 04:37:24 PM PDT 24
Peak memory	206412 kb
Host	smart-6c0d860e-faf3-449c-9c06-23624b7c6fe0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1471625430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1471625430
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2183937132
Short name	T82
Test name
Test status
Simulation time	112014669 ps
CPU time	1.37 seconds
Started	Jul 19 04:37:03 PM PDT 24
Finished	Jul 19 04:37:22 PM PDT 24
Peak memory	214660 kb
Host	smart-350d1e24-1648-4be5-a023-1605546005b0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183937132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd ev_csr_mem_rw_with_rand_reset.2183937132
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1138590048
Short name	T103
Test name
Test status
Simulation time	113275212 ps
CPU time	1.02 seconds
Started	Jul 19 04:37:02 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	206384 kb
Host	smart-99012c9d-0e91-4568-ac90-71bd7ab530cb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1138590048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1138590048
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1322092090
Short name	T108
Test name
Test status
Simulation time	232337334 ps
CPU time	2.88 seconds
Started	Jul 19 04:37:02 PM PDT 24
Finished	Jul 19 04:37:22 PM PDT 24
Peak memory	214652 kb
Host	smart-39272280-9dc5-4d4f-9b4f-6414ea90ffb1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1322092090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1322092090
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.588150701
Short name	T156
Test name
Test status
Simulation time	207044252 ps
CPU time	1.8 seconds
Started	Jul 19 04:37:03 PM PDT 24
Finished	Jul 19 04:37:22 PM PDT 24
Peak memory	218396 kb
Host	smart-f9519b47-d5a0-4498-bfbc-ba7da085d5ff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588150701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde v_csr_mem_rw_with_rand_reset.588150701
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4225493540
Short name	T31
Test name
Test status
Simulation time	48586175 ps
CPU time	1.06 seconds
Started	Jul 19 04:37:04 PM PDT 24
Finished	Jul 19 04:37:22 PM PDT 24
Peak memory	206336 kb
Host	smart-c0a235a1-92ea-4fec-b4fa-81c2aa480133
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4225493540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.4225493540
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1350300420
Short name	T68
Test name
Test status
Simulation time	32890091 ps
CPU time	0.68 seconds
Started	Jul 19 04:37:03 PM PDT 24
Finished	Jul 19 04:37:21 PM PDT 24
Peak memory	206212 kb
Host	smart-2be13ef0-2bc1-407e-8b6c-6923de8b9059
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1350300420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1350300420
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3805691972
Short name	T98
Test name
Test status
Simulation time	205749126 ps
CPU time	1.76 seconds
Started	Jul 19 04:37:04 PM PDT 24
Finished	Jul 19 04:37:22 PM PDT 24
Peak memory	206392 kb
Host	smart-3f72feab-8539-4996-8931-e5ae9b1779f3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3805691972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3805691972
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.719117725
Short name	T21
Test name
Test status
Simulation time	64175721 ps
CPU time	1.27 seconds
Started	Jul 19 04:37:02 PM PDT 24
Finished	Jul 19 04:37:21 PM PDT 24
Peak memory	206428 kb
Host	smart-49a4626f-7b10-42b4-9332-84d0203d40d0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=719117725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.719117725
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4202310358
Short name	T25
Test name
Test status
Simulation time	681367634 ps
CPU time	4.36 seconds
Started	Jul 19 04:37:06 PM PDT 24
Finished	Jul 19 04:37:26 PM PDT 24
Peak memory	206480 kb
Host	smart-81f1eec5-efcc-4fea-b368-828737b12a33
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4202310358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.4202310358
Directory	/workspace/12.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2316740893
Short name	T1
Test name
Test status
Simulation time	121635863 ps
CPU time	2.95 seconds
Started	Jul 19 04:37:10 PM PDT 24
Finished	Jul 19 04:37:29 PM PDT 24
Peak memory	214644 kb
Host	smart-1ed2571a-83b8-4db4-af39-d7203f076aed
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316740893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd ev_csr_mem_rw_with_rand_reset.2316740893
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2998993092
Short name	T29
Test name
Test status
Simulation time	138680586 ps
CPU time	1.09 seconds
Started	Jul 19 04:37:09 PM PDT 24
Finished	Jul 19 04:37:26 PM PDT 24
Peak memory	206360 kb
Host	smart-018aa99c-7fac-4562-b66d-76899281f435
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2998993092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2998993092
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3839700630
Short name	T5
Test name
Test status
Simulation time	48181201 ps
CPU time	0.68 seconds
Started	Jul 19 04:37:02 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	206224 kb
Host	smart-8459f070-293f-440c-9eab-767621f1ae39
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3839700630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3839700630
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.928196309
Short name	T46
Test name
Test status
Simulation time	161785030 ps
CPU time	1.5 seconds
Started	Jul 19 04:37:09 PM PDT 24
Finished	Jul 19 04:37:27 PM PDT 24
Peak memory	206456 kb
Host	smart-6bee9482-a340-40a2-a73b-33330e065d22
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=928196309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.928196309
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4175470885
Short name	T112
Test name
Test status
Simulation time	147193466 ps
CPU time	1.81 seconds
Started	Jul 19 04:37:02 PM PDT 24
Finished	Jul 19 04:37:21 PM PDT 24
Peak memory	222016 kb
Host	smart-6ef4673a-a957-48e0-97da-7332ca75b69f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4175470885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4175470885
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3696504857
Short name	T114
Test name
Test status
Simulation time	155055024 ps
CPU time	1.36 seconds
Started	Jul 19 04:37:19 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	214712 kb
Host	smart-f8769203-ead7-4966-8064-9b58e49db9fc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696504857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd ev_csr_mem_rw_with_rand_reset.3696504857
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.862273235
Short name	T102
Test name
Test status
Simulation time	76983964 ps
CPU time	1.01 seconds
Started	Jul 19 04:37:17 PM PDT 24
Finished	Jul 19 04:37:31 PM PDT 24
Peak memory	206324 kb
Host	smart-86463718-e1dd-4d66-ad83-d51be722167e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=862273235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.862273235
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.762206953
Short name	T161
Test name
Test status
Simulation time	161303145 ps
CPU time	1.7 seconds
Started	Jul 19 04:37:21 PM PDT 24
Finished	Jul 19 04:37:33 PM PDT 24
Peak memory	206392 kb
Host	smart-e9cb3600-9705-428e-a81f-c89972126a49
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=762206953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.762206953
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3564640259
Short name	T129
Test name
Test status
Simulation time	237942419 ps
CPU time	2.41 seconds
Started	Jul 19 04:37:16 PM PDT 24
Finished	Jul 19 04:37:31 PM PDT 24
Peak memory	206640 kb
Host	smart-00debb81-0d1c-48b3-91f3-06f5434be000
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3564640259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3564640259
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2800420155
Short name	T57
Test name
Test status
Simulation time	1641464632 ps
CPU time	5.14 seconds
Started	Jul 19 04:37:11 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206396 kb
Host	smart-e7804369-9dc1-41b2-80ca-a0fe374db735
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2800420155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2800420155
Directory	/workspace/14.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.887795920
Short name	T2
Test name
Test status
Simulation time	146287661 ps
CPU time	1.89 seconds
Started	Jul 19 04:37:10 PM PDT 24
Finished	Jul 19 04:37:28 PM PDT 24
Peak memory	214672 kb
Host	smart-346b1a8f-4114-41ad-b3ff-3ab6e74dd406
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887795920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde v_csr_mem_rw_with_rand_reset.887795920
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.465380924
Short name	T173
Test name
Test status
Simulation time	63882410 ps
CPU time	0.79 seconds
Started	Jul 19 04:37:12 PM PDT 24
Finished	Jul 19 04:37:28 PM PDT 24
Peak memory	206236 kb
Host	smart-37679466-625c-4dda-b1f0-57c2207edba4
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=465380924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.465380924
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.1119260255
Short name	T134
Test name
Test status
Simulation time	50075903 ps
CPU time	0.68 seconds
Started	Jul 19 04:37:19 PM PDT 24
Finished	Jul 19 04:37:31 PM PDT 24
Peak memory	206148 kb
Host	smart-53532abd-997c-489a-81d6-46ab7995bdbd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1119260255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1119260255
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.19387841
Short name	T6
Test name
Test status
Simulation time	180082503 ps
CPU time	1.64 seconds
Started	Jul 19 04:37:19 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206380 kb
Host	smart-4692edd4-e6b3-4bd0-8ff3-9cfdeb713f53
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=19387841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.19387841
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2717161543
Short name	T170
Test name
Test status
Simulation time	141609480 ps
CPU time	1.76 seconds
Started	Jul 19 04:37:11 PM PDT 24
Finished	Jul 19 04:37:28 PM PDT 24
Peak memory	206448 kb
Host	smart-e0602541-1ef1-48ee-a1ae-1240348ea06f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2717161543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2717161543
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.21940791
Short name	T60
Test name
Test status
Simulation time	742115740 ps
CPU time	4.45 seconds
Started	Jul 19 04:37:11 PM PDT 24
Finished	Jul 19 04:37:31 PM PDT 24
Peak memory	206592 kb
Host	smart-7c4b555c-8000-4235-a4b1-2723c975886d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=21940791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.21940791
Directory	/workspace/15.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2862352536
Short name	T79
Test name
Test status
Simulation time	150492697 ps
CPU time	1.74 seconds
Started	Jul 19 04:37:11 PM PDT 24
Finished	Jul 19 04:37:28 PM PDT 24
Peak memory	214780 kb
Host	smart-47919586-3cc0-44f7-85de-7e7f004b7e32
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862352536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd ev_csr_mem_rw_with_rand_reset.2862352536
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.4133093216
Short name	T81
Test name
Test status
Simulation time	87094602 ps
CPU time	0.95 seconds
Started	Jul 19 04:37:16 PM PDT 24
Finished	Jul 19 04:37:30 PM PDT 24
Peak memory	206324 kb
Host	smart-d954018c-b377-435a-bb96-71b0a73fc2ec
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4133093216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.4133093216
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1078961707
Short name	T55
Test name
Test status
Simulation time	72153904 ps
CPU time	0.73 seconds
Started	Jul 19 04:37:11 PM PDT 24
Finished	Jul 19 04:37:27 PM PDT 24
Peak memory	206192 kb
Host	smart-78f4a421-5e4b-4b03-b22d-8ad8ad171b95
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1078961707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1078961707
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3610332061
Short name	T150
Test name
Test status
Simulation time	108818079 ps
CPU time	1.13 seconds
Started	Jul 19 04:37:11 PM PDT 24
Finished	Jul 19 04:37:28 PM PDT 24
Peak memory	206468 kb
Host	smart-2ff64076-639a-4fe8-a347-1adf8d480b7f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3610332061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3610332061
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3907148190
Short name	T123
Test name
Test status
Simulation time	87221886 ps
CPU time	1.59 seconds
Started	Jul 19 04:37:12 PM PDT 24
Finished	Jul 19 04:37:29 PM PDT 24
Peak memory	206512 kb
Host	smart-f87da389-a7af-4508-9bd8-cf2b2e6d9f32
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3907148190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3907148190
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.581971144
Short name	T16
Test name
Test status
Simulation time	512430679 ps
CPU time	2.71 seconds
Started	Jul 19 04:37:19 PM PDT 24
Finished	Jul 19 04:37:33 PM PDT 24
Peak memory	206404 kb
Host	smart-6c66f886-482c-47ce-9ab4-ba28f4fbb7d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=581971144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.581971144
Directory	/workspace/16.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3244256771
Short name	T20
Test name
Test status
Simulation time	125958239 ps
CPU time	1.74 seconds
Started	Jul 19 04:37:10 PM PDT 24
Finished	Jul 19 04:37:28 PM PDT 24
Peak memory	214908 kb
Host	smart-ca719169-ad07-4875-b1e4-d27444d0edbf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244256771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd ev_csr_mem_rw_with_rand_reset.3244256771
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2415552916
Short name	T44
Test name
Test status
Simulation time	82879021 ps
CPU time	1 seconds
Started	Jul 19 04:37:12 PM PDT 24
Finished	Jul 19 04:37:28 PM PDT 24
Peak memory	206320 kb
Host	smart-63a45e6b-8f8f-4795-95b2-cb257be69085
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2415552916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2415552916
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2149997408
Short name	T92
Test name
Test status
Simulation time	55478552 ps
CPU time	0.73 seconds
Started	Jul 19 04:37:12 PM PDT 24
Finished	Jul 19 04:37:28 PM PDT 24
Peak memory	206232 kb
Host	smart-ed366702-e1da-490c-9076-a6e952fcdd26
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2149997408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2149997408
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1545294537
Short name	T45
Test name
Test status
Simulation time	109755176 ps
CPU time	1.15 seconds
Started	Jul 19 04:37:11 PM PDT 24
Finished	Jul 19 04:37:28 PM PDT 24
Peak memory	206428 kb
Host	smart-a7ced31a-e8a2-4c94-b397-c5c7ed4b68f5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1545294537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1545294537
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.360093724
Short name	T124
Test name
Test status
Simulation time	244814734 ps
CPU time	2.31 seconds
Started	Jul 19 04:37:22 PM PDT 24
Finished	Jul 19 04:37:35 PM PDT 24
Peak memory	206464 kb
Host	smart-89f57264-ef32-4bb4-9ceb-ee2e55ae9e25
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=360093724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.360093724
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3831952823
Short name	T26
Test name
Test status
Simulation time	452406421 ps
CPU time	2.8 seconds
Started	Jul 19 04:37:16 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206424 kb
Host	smart-7745e040-c234-4bfa-9e9c-92adb75c1fe6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3831952823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3831952823
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1940681776
Short name	T132
Test name
Test status
Simulation time	91597944 ps
CPU time	2.05 seconds
Started	Jul 19 04:37:19 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	214648 kb
Host	smart-52f945dd-3f1c-41f4-bc98-8ad8c7d335f4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940681776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd ev_csr_mem_rw_with_rand_reset.1940681776
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3583006937
Short name	T118
Test name
Test status
Simulation time	110922149 ps
CPU time	1.05 seconds
Started	Jul 19 04:37:12 PM PDT 24
Finished	Jul 19 04:37:28 PM PDT 24
Peak memory	206336 kb
Host	smart-709ea031-4b6a-4f31-8f75-378f1bd63021
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3583006937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3583006937
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.34966771
Short name	T119
Test name
Test status
Simulation time	39638941 ps
CPU time	0.69 seconds
Started	Jul 19 04:37:22 PM PDT 24
Finished	Jul 19 04:37:33 PM PDT 24
Peak memory	206184 kb
Host	smart-e137ff34-f48f-4fb8-aaf9-b104ab9d681a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=34966771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.34966771
Directory	/workspace/18.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2983872536
Short name	T154
Test name
Test status
Simulation time	305753764 ps
CPU time	2.14 seconds
Started	Jul 19 04:37:19 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206324 kb
Host	smart-d9945b86-f3c6-46e9-8b0c-9972434da6dc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2983872536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.2983872536
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2813904257
Short name	T127
Test name
Test status
Simulation time	101987200 ps
CPU time	2.87 seconds
Started	Jul 19 04:37:19 PM PDT 24
Finished	Jul 19 04:37:33 PM PDT 24
Peak memory	222072 kb
Host	smart-b434f5da-25b5-444e-9e02-83b35fd07512
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2813904257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2813904257
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1608302655
Short name	T66
Test name
Test status
Simulation time	934154932 ps
CPU time	2.99 seconds
Started	Jul 19 04:37:11 PM PDT 24
Finished	Jul 19 04:37:29 PM PDT 24
Peak memory	206360 kb
Host	smart-f34b4cdf-45a4-428d-b272-049ac592cf58
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1608302655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1608302655
Directory	/workspace/18.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.833870913
Short name	T18
Test name
Test status
Simulation time	92604370 ps
CPU time	1.18 seconds
Started	Jul 19 04:37:18 PM PDT 24
Finished	Jul 19 04:37:31 PM PDT 24
Peak memory	214592 kb
Host	smart-45bc1943-621e-4158-b657-3213167cce85
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833870913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde v_csr_mem_rw_with_rand_reset.833870913
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3569001440
Short name	T42
Test name
Test status
Simulation time	46263454 ps
CPU time	0.83 seconds
Started	Jul 19 04:37:19 PM PDT 24
Finished	Jul 19 04:37:31 PM PDT 24
Peak memory	206212 kb
Host	smart-12cc6935-0b56-497b-93ea-9294c45c5463
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3569001440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3569001440
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3979421347
Short name	T74
Test name
Test status
Simulation time	58798399 ps
CPU time	0.71 seconds
Started	Jul 19 04:37:17 PM PDT 24
Finished	Jul 19 04:37:30 PM PDT 24
Peak memory	206188 kb
Host	smart-5f3fa7eb-69a9-44ff-bbf2-c3c90586b873
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3979421347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3979421347
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2297480833
Short name	T135
Test name
Test status
Simulation time	105121874 ps
CPU time	1.12 seconds
Started	Jul 19 04:37:25 PM PDT 24
Finished	Jul 19 04:37:35 PM PDT 24
Peak memory	206432 kb
Host	smart-aeae08c6-0002-4112-8519-1a26acfd1cec
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2297480833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2297480833
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1572507578
Short name	T155
Test name
Test status
Simulation time	221646204 ps
CPU time	2.45 seconds
Started	Jul 19 04:37:13 PM PDT 24
Finished	Jul 19 04:37:30 PM PDT 24
Peak memory	214676 kb
Host	smart-c6e5a36e-81ca-4a8d-a22b-d32ce58083da
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1572507578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1572507578
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2900150277
Short name	T142
Test name
Test status
Simulation time	279292781 ps
CPU time	2.27 seconds
Started	Jul 19 04:37:09 PM PDT 24
Finished	Jul 19 04:37:28 PM PDT 24
Peak memory	206460 kb
Host	smart-44b27d41-e68d-4f80-b966-c244cf9ceb60
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2900150277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2900150277
Directory	/workspace/19.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.82088546
Short name	T133
Test name
Test status
Simulation time	203372953 ps
CPU time	1.97 seconds
Started	Jul 19 04:36:42 PM PDT 24
Finished	Jul 19 04:37:13 PM PDT 24
Peak memory	206388 kb
Host	smart-7c221497-e6e5-4add-92cd-9058267faf06
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=82088546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.82088546
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1144498938
Short name	T160
Test name
Test status
Simulation time	1735284879 ps
CPU time	9.01 seconds
Started	Jul 19 04:36:55 PM PDT 24
Finished	Jul 19 04:37:26 PM PDT 24
Peak memory	206284 kb
Host	smart-b3207fd7-494a-4eef-8275-40a7979bbbba
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1144498938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1144498938
Directory	/workspace/2.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3580892951
Short name	T8
Test name
Test status
Simulation time	51736583 ps
CPU time	0.77 seconds
Started	Jul 19 04:36:41 PM PDT 24
Finished	Jul 19 04:37:12 PM PDT 24
Peak memory	206260 kb
Host	smart-21d52919-12e4-4015-b20a-64577c47f227
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3580892951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3580892951
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1800487474
Short name	T97
Test name
Test status
Simulation time	249404284 ps
CPU time	1.85 seconds
Started	Jul 19 04:36:34 PM PDT 24
Finished	Jul 19 04:37:10 PM PDT 24
Peak memory	219104 kb
Host	smart-ff250e0c-f787-4a68-8ebd-a0db123b4e61
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800487474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde v_csr_mem_rw_with_rand_reset.1800487474
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.463417658
Short name	T41
Test name
Test status
Simulation time	50152143 ps
CPU time	0.95 seconds
Started	Jul 19 04:36:36 PM PDT 24
Finished	Jul 19 04:37:10 PM PDT 24
Peak memory	206376 kb
Host	smart-2c385e8f-1e80-46af-a1e9-8685a22566ed
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=463417658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.463417658
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.3141346980
Short name	T95
Test name
Test status
Simulation time	36010739 ps
CPU time	0.68 seconds
Started	Jul 19 04:36:40 PM PDT 24
Finished	Jul 19 04:37:11 PM PDT 24
Peak memory	206196 kb
Host	smart-965f9d78-b732-4904-91ed-b4f02df1eb59
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3141346980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3141346980
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.379932253
Short name	T24
Test name
Test status
Simulation time	253505789 ps
CPU time	2.43 seconds
Started	Jul 19 04:36:37 PM PDT 24
Finished	Jul 19 04:37:12 PM PDT 24
Peak memory	215904 kb
Host	smart-a6efbc5f-c75f-4f3c-92a7-ed0797e52086
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=379932253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.379932253
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3067539182
Short name	T168
Test name
Test status
Simulation time	250649103 ps
CPU time	2.59 seconds
Started	Jul 19 04:36:46 PM PDT 24
Finished	Jul 19 04:37:15 PM PDT 24
Peak memory	206308 kb
Host	smart-05fafcbe-ea83-47cd-9be2-c173f7e440ad
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3067539182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3067539182
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.572438882
Short name	T165
Test name
Test status
Simulation time	227085924 ps
CPU time	1.51 seconds
Started	Jul 19 04:36:48 PM PDT 24
Finished	Jul 19 04:37:14 PM PDT 24
Peak memory	206348 kb
Host	smart-81f4e152-3309-43bb-8687-50efce826a40
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=572438882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.572438882
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1846499846
Short name	T51
Test name
Test status
Simulation time	282437141 ps
CPU time	2.9 seconds
Started	Jul 19 04:36:40 PM PDT 24
Finished	Jul 19 04:37:13 PM PDT 24
Peak memory	214720 kb
Host	smart-43f982ce-3a2f-4924-a1be-b5eb42bd94c9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1846499846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1846499846
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3897060442
Short name	T58
Test name
Test status
Simulation time	1613250226 ps
CPU time	5.89 seconds
Started	Jul 19 04:36:37 PM PDT 24
Finished	Jul 19 04:37:15 PM PDT 24
Peak memory	206576 kb
Host	smart-33881a8f-e0b2-4ef3-b868-39796420b624
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3897060442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3897060442
Directory	/workspace/2.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.162006595
Short name	T93
Test name
Test status
Simulation time	55589975 ps
CPU time	0.67 seconds
Started	Jul 19 04:37:22 PM PDT 24
Finished	Jul 19 04:37:33 PM PDT 24
Peak memory	206196 kb
Host	smart-a6c2929b-ddf0-4a5b-b516-d031b9e321e1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=162006595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.162006595
Directory	/workspace/20.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.4213297540
Short name	T14
Test name
Test status
Simulation time	48034395 ps
CPU time	0.72 seconds
Started	Jul 19 04:37:21 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206248 kb
Host	smart-8b5874d6-a6d8-4181-af5b-e4a782c51d44
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4213297540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4213297540
Directory	/workspace/21.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.2664085477
Short name	T121
Test name
Test status
Simulation time	52536993 ps
CPU time	0.78 seconds
Started	Jul 19 04:37:19 PM PDT 24
Finished	Jul 19 04:37:31 PM PDT 24
Peak memory	206420 kb
Host	smart-4cb338ee-88c9-4dde-87ce-3c27237d6043
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2664085477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2664085477
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.3654400186
Short name	T13
Test name
Test status
Simulation time	38378288 ps
CPU time	0.67 seconds
Started	Jul 19 04:37:25 PM PDT 24
Finished	Jul 19 04:37:35 PM PDT 24
Peak memory	206184 kb
Host	smart-91443d83-69d4-436c-bf59-ad42ecf0a01a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3654400186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3654400186
Directory	/workspace/23.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.2651076660
Short name	T85
Test name
Test status
Simulation time	54881236 ps
CPU time	0.7 seconds
Started	Jul 19 04:37:21 PM PDT 24
Finished	Jul 19 04:37:33 PM PDT 24
Peak memory	206224 kb
Host	smart-c5b07a76-0187-48c2-90ff-5cc9c09447bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2651076660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2651076660
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.4221380458
Short name	T80
Test name
Test status
Simulation time	42064504 ps
CPU time	0.66 seconds
Started	Jul 19 04:37:25 PM PDT 24
Finished	Jul 19 04:37:35 PM PDT 24
Peak memory	206224 kb
Host	smart-dff48e4f-0817-45e0-8c93-8d3b6913fd75
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4221380458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4221380458
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2891923567
Short name	T3
Test name
Test status
Simulation time	43242285 ps
CPU time	0.71 seconds
Started	Jul 19 04:37:22 PM PDT 24
Finished	Jul 19 04:37:33 PM PDT 24
Peak memory	206204 kb
Host	smart-3e73dd14-bb22-4191-9ab0-1364fdfb2989
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2891923567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2891923567
Directory	/workspace/27.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.2455608018
Short name	T75
Test name
Test status
Simulation time	66944018 ps
CPU time	0.72 seconds
Started	Jul 19 04:37:23 PM PDT 24
Finished	Jul 19 04:37:34 PM PDT 24
Peak memory	206208 kb
Host	smart-910c38a4-a273-4279-b1ed-cf9b15e4110c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2455608018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2455608018
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.1117712710
Short name	T104
Test name
Test status
Simulation time	30972025 ps
CPU time	0.71 seconds
Started	Jul 19 04:37:24 PM PDT 24
Finished	Jul 19 04:37:35 PM PDT 24
Peak memory	206208 kb
Host	smart-7896aa0a-59b7-42f3-83f3-06cb5b55fc0f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1117712710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1117712710
Directory	/workspace/29.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1622306522
Short name	T34
Test name
Test status
Simulation time	366030349 ps
CPU time	3.45 seconds
Started	Jul 19 04:36:42 PM PDT 24
Finished	Jul 19 04:37:15 PM PDT 24
Peak memory	206504 kb
Host	smart-c3883f4e-9c8e-4ceb-b09e-e186c06c4439
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1622306522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1622306522
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4052886489
Short name	T47
Test name
Test status
Simulation time	1019289521 ps
CPU time	4.86 seconds
Started	Jul 19 04:36:44 PM PDT 24
Finished	Jul 19 04:37:17 PM PDT 24
Peak memory	206380 kb
Host	smart-45c5d38e-7b3b-4c5d-9072-9ee8f9a9792a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4052886489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.4052886489
Directory	/workspace/3.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3279654807
Short name	T10
Test name
Test status
Simulation time	62789545 ps
CPU time	0.81 seconds
Started	Jul 19 04:36:47 PM PDT 24
Finished	Jul 19 04:37:13 PM PDT 24
Peak memory	206228 kb
Host	smart-acd6648c-05f4-49a7-aafc-fcd85369e592
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3279654807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3279654807
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.758347704
Short name	T23
Test name
Test status
Simulation time	184849688 ps
CPU time	1.97 seconds
Started	Jul 19 04:36:55 PM PDT 24
Finished	Jul 19 04:37:19 PM PDT 24
Peak memory	214580 kb
Host	smart-96667814-78d4-4cea-86c0-4b5f44866d57
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758347704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev _csr_mem_rw_with_rand_reset.758347704
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3718935760
Short name	T122
Test name
Test status
Simulation time	71289378 ps
CPU time	0.88 seconds
Started	Jul 19 04:36:41 PM PDT 24
Finished	Jul 19 04:37:12 PM PDT 24
Peak memory	206256 kb
Host	smart-48de74b0-ef82-4fc2-9687-1d84921c8fca
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3718935760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3718935760
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.2887472502
Short name	T147
Test name
Test status
Simulation time	50972086 ps
CPU time	0.66 seconds
Started	Jul 19 04:36:45 PM PDT 24
Finished	Jul 19 04:37:13 PM PDT 24
Peak memory	206196 kb
Host	smart-db2f4d69-599f-41a9-b361-4a6a97e9031e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2887472502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2887472502
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3666760228
Short name	T166
Test name
Test status
Simulation time	111876439 ps
CPU time	1.52 seconds
Started	Jul 19 04:36:44 PM PDT 24
Finished	Jul 19 04:37:13 PM PDT 24
Peak memory	222816 kb
Host	smart-f8015b1a-0ddd-4d54-93c4-17cdeb55d831
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3666760228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3666760228
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.239931004
Short name	T158
Test name
Test status
Simulation time	371643093 ps
CPU time	2.75 seconds
Started	Jul 19 04:36:44 PM PDT 24
Finished	Jul 19 04:37:15 PM PDT 24
Peak memory	206280 kb
Host	smart-43520b81-6bb6-47ef-b3fb-2e30406ca909
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=239931004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.239931004
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4291996625
Short name	T110
Test name
Test status
Simulation time	87242173 ps
CPU time	1.35 seconds
Started	Jul 19 04:36:45 PM PDT 24
Finished	Jul 19 04:37:14 PM PDT 24
Peak memory	206464 kb
Host	smart-d0b2375e-6812-4a90-a4f9-3ee6ffd20ede
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4291996625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.4291996625
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.4175343923
Short name	T126
Test name
Test status
Simulation time	42209995 ps
CPU time	0.69 seconds
Started	Jul 19 04:37:23 PM PDT 24
Finished	Jul 19 04:37:33 PM PDT 24
Peak memory	206184 kb
Host	smart-59c9d145-76ec-4cb5-a3a5-6815633b12ea
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4175343923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.4175343923
Directory	/workspace/30.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.1537710058
Short name	T169
Test name
Test status
Simulation time	93259941 ps
CPU time	0.72 seconds
Started	Jul 19 04:37:20 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206368 kb
Host	smart-df731f2f-5afb-43e1-9b51-efc638e8d0bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1537710058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1537710058
Directory	/workspace/31.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.637185541
Short name	T86
Test name
Test status
Simulation time	34033499 ps
CPU time	0.65 seconds
Started	Jul 19 04:37:21 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206188 kb
Host	smart-faad5d3f-41e1-4ded-9ac8-75a40b2e9872
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=637185541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.637185541
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.963141365
Short name	T130
Test name
Test status
Simulation time	42679778 ps
CPU time	0.67 seconds
Started	Jul 19 04:37:21 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206192 kb
Host	smart-bcdb3e6b-3cef-418b-ac78-137e61b714a7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=963141365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.963141365
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.2241129065
Short name	T148
Test name
Test status
Simulation time	43275047 ps
CPU time	0.69 seconds
Started	Jul 19 04:37:21 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206216 kb
Host	smart-faf8ee1c-7682-41b7-a62f-75c1d1a81819
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2241129065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2241129065
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.448234377
Short name	T83
Test name
Test status
Simulation time	39178564 ps
CPU time	0.66 seconds
Started	Jul 19 04:37:20 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206212 kb
Host	smart-ad086b16-19c9-460d-a0fe-7ae354fa36f9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=448234377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.448234377
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.128732157
Short name	T125
Test name
Test status
Simulation time	33778287 ps
CPU time	0.68 seconds
Started	Jul 19 04:37:21 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206180 kb
Host	smart-c9fd7cbb-8e21-450f-aec9-38a61692693c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=128732157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.128732157
Directory	/workspace/36.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2071393131
Short name	T76
Test name
Test status
Simulation time	57006061 ps
CPU time	0.7 seconds
Started	Jul 19 04:37:22 PM PDT 24
Finished	Jul 19 04:37:33 PM PDT 24
Peak memory	206204 kb
Host	smart-0a4d80e3-5951-4050-bc8b-21986b4ea92b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2071393131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2071393131
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.993190581
Short name	T15
Test name
Test status
Simulation time	59753059 ps
CPU time	0.67 seconds
Started	Jul 19 04:37:23 PM PDT 24
Finished	Jul 19 04:37:34 PM PDT 24
Peak memory	206196 kb
Host	smart-3f5beeb8-069a-4934-9e42-b1493b66cba3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=993190581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.993190581
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3351066205
Short name	T137
Test name
Test status
Simulation time	69178031 ps
CPU time	0.75 seconds
Started	Jul 19 04:37:23 PM PDT 24
Finished	Jul 19 04:37:34 PM PDT 24
Peak memory	206192 kb
Host	smart-085fdc7a-2af7-4047-8f5a-8aa35c067de2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3351066205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3351066205
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3598189184
Short name	T116
Test name
Test status
Simulation time	125317535 ps
CPU time	3.1 seconds
Started	Jul 19 04:36:52 PM PDT 24
Finished	Jul 19 04:37:17 PM PDT 24
Peak memory	206332 kb
Host	smart-99b679d1-0acf-4279-bad0-93005d28b615
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3598189184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3598189184
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3394574423
Short name	T163
Test name
Test status
Simulation time	893315342 ps
CPU time	7.17 seconds
Started	Jul 19 04:36:53 PM PDT 24
Finished	Jul 19 04:37:21 PM PDT 24
Peak memory	206328 kb
Host	smart-49a74057-8706-45d8-80fe-8677af61c3a0
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3394574423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3394574423
Directory	/workspace/4.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3964683331
Short name	T72
Test name
Test status
Simulation time	139039115 ps
CPU time	1.74 seconds
Started	Jul 19 04:36:57 PM PDT 24
Finished	Jul 19 04:37:19 PM PDT 24
Peak memory	214612 kb
Host	smart-2a73cd8b-ac1e-4f6d-80d6-23993a496341
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964683331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde v_csr_mem_rw_with_rand_reset.3964683331
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2349457856
Short name	T141
Test name
Test status
Simulation time	116450354 ps
CPU time	0.79 seconds
Started	Jul 19 04:36:51 PM PDT 24
Finished	Jul 19 04:37:14 PM PDT 24
Peak memory	206256 kb
Host	smart-fdbde19b-f66f-4ba9-a02f-6a1c6b932a5b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2349457856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2349457856
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.1959374241
Short name	T89
Test name
Test status
Simulation time	35345725 ps
CPU time	0.69 seconds
Started	Jul 19 04:36:54 PM PDT 24
Finished	Jul 19 04:37:17 PM PDT 24
Peak memory	206204 kb
Host	smart-ee6c17fe-b389-48d8-84cd-003635106195
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1959374241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1959374241
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2299099960
Short name	T43
Test name
Test status
Simulation time	124497100 ps
CPU time	2.33 seconds
Started	Jul 19 04:36:55 PM PDT 24
Finished	Jul 19 04:37:19 PM PDT 24
Peak memory	214780 kb
Host	smart-1a49fbbd-0b96-4299-8f80-2b39be7b9a00
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2299099960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2299099960
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1773804982
Short name	T105
Test name
Test status
Simulation time	371641747 ps
CPU time	2.52 seconds
Started	Jul 19 04:36:53 PM PDT 24
Finished	Jul 19 04:37:18 PM PDT 24
Peak memory	206320 kb
Host	smart-766a7740-7056-4cd1-af2b-2a7caf0de854
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1773804982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1773804982
Directory	/workspace/4.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4059776174
Short name	T172
Test name
Test status
Simulation time	243462424 ps
CPU time	1.68 seconds
Started	Jul 19 04:36:51 PM PDT 24
Finished	Jul 19 04:37:15 PM PDT 24
Peak memory	206448 kb
Host	smart-a799c133-dcde-449b-8d45-f0d5e5a1d58c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4059776174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.4059776174
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3390299701
Short name	T149
Test name
Test status
Simulation time	1696969722 ps
CPU time	6.2 seconds
Started	Jul 19 04:36:46 PM PDT 24
Finished	Jul 19 04:37:18 PM PDT 24
Peak memory	206384 kb
Host	smart-84f70875-4d73-464c-b840-4ae81425976a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3390299701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3390299701
Directory	/workspace/4.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.409954018
Short name	T70
Test name
Test status
Simulation time	35559334 ps
CPU time	0.68 seconds
Started	Jul 19 04:37:22 PM PDT 24
Finished	Jul 19 04:37:33 PM PDT 24
Peak memory	206228 kb
Host	smart-6e019759-b9e0-4150-8484-d8073ead7cce
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=409954018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.409954018
Directory	/workspace/40.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.2654332410
Short name	T35
Test name
Test status
Simulation time	39971580 ps
CPU time	0.71 seconds
Started	Jul 19 04:37:20 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206204 kb
Host	smart-697bd993-a9cd-4c0f-b072-649f5cf619bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2654332410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2654332410
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.3626516107
Short name	T54
Test name
Test status
Simulation time	63233500 ps
CPU time	0.71 seconds
Started	Jul 19 04:37:26 PM PDT 24
Finished	Jul 19 04:37:35 PM PDT 24
Peak memory	206200 kb
Host	smart-913747c0-cd98-4259-bd18-a5a19f630d3a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3626516107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3626516107
Directory	/workspace/44.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.4106122161
Short name	T53
Test name
Test status
Simulation time	66748938 ps
CPU time	0.66 seconds
Started	Jul 19 04:37:23 PM PDT 24
Finished	Jul 19 04:37:34 PM PDT 24
Peak memory	206244 kb
Host	smart-17c5ecc8-fb45-423b-b354-f7f413992f22
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4106122161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.4106122161
Directory	/workspace/45.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.190206188
Short name	T120
Test name
Test status
Simulation time	40639368 ps
CPU time	0.68 seconds
Started	Jul 19 04:37:22 PM PDT 24
Finished	Jul 19 04:37:33 PM PDT 24
Peak memory	206200 kb
Host	smart-eeef5679-234c-4db9-98d1-4eb8ec21940e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=190206188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.190206188
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.2216326237
Short name	T73
Test name
Test status
Simulation time	62323837 ps
CPU time	0.74 seconds
Started	Jul 19 04:37:23 PM PDT 24
Finished	Jul 19 04:37:34 PM PDT 24
Peak memory	206216 kb
Host	smart-4e67246d-95b2-43c3-8542-3fef4a66ceb7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2216326237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2216326237
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.3287691723
Short name	T175
Test name
Test status
Simulation time	41273210 ps
CPU time	0.68 seconds
Started	Jul 19 04:37:24 PM PDT 24
Finished	Jul 19 04:37:35 PM PDT 24
Peak memory	206200 kb
Host	smart-ff145ce5-0855-4185-904f-8a92ca7c21fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3287691723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3287691723
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.197747200
Short name	T107
Test name
Test status
Simulation time	39666699 ps
CPU time	0.7 seconds
Started	Jul 19 04:37:20 PM PDT 24
Finished	Jul 19 04:37:32 PM PDT 24
Peak memory	206200 kb
Host	smart-30b52ef5-1dac-416c-85a8-647c1012c218
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=197747200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.197747200
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.760966719
Short name	T101
Test name
Test status
Simulation time	100562380 ps
CPU time	2.59 seconds
Started	Jul 19 04:36:56 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	214724 kb
Host	smart-d1d3e0d5-0809-4a67-a378-3d682061d727
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760966719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev _csr_mem_rw_with_rand_reset.760966719
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1445707641
Short name	T90
Test name
Test status
Simulation time	45314908 ps
CPU time	0.82 seconds
Started	Jul 19 04:36:54 PM PDT 24
Finished	Jul 19 04:37:17 PM PDT 24
Peak memory	206228 kb
Host	smart-218cfdf8-c3d1-4483-8025-56d4e74dd0c6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1445707641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1445707641
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.673438229
Short name	T167
Test name
Test status
Simulation time	76751061 ps
CPU time	0.72 seconds
Started	Jul 19 04:36:55 PM PDT 24
Finished	Jul 19 04:37:17 PM PDT 24
Peak memory	206212 kb
Host	smart-fd74c8fe-6b1e-4b87-945a-000cff49b2bf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=673438229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.673438229
Directory	/workspace/5.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1131093155
Short name	T77
Test name
Test status
Simulation time	400485538 ps
CPU time	2.26 seconds
Started	Jul 19 04:36:55 PM PDT 24
Finished	Jul 19 04:37:19 PM PDT 24
Peak memory	206496 kb
Host	smart-e6c039c7-13ea-4bc6-9444-990103dc62a1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1131093155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1131093155
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3893408171
Short name	T22
Test name
Test status
Simulation time	204678380 ps
CPU time	2.17 seconds
Started	Jul 19 04:36:53 PM PDT 24
Finished	Jul 19 04:37:16 PM PDT 24
Peak memory	222688 kb
Host	smart-cceb684e-8602-4053-9999-42d1e5fac08a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3893408171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3893408171
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2879088906
Short name	T63
Test name
Test status
Simulation time	691982298 ps
CPU time	4.63 seconds
Started	Jul 19 04:36:55 PM PDT 24
Finished	Jul 19 04:37:21 PM PDT 24
Peak memory	206408 kb
Host	smart-2d2becc2-eaa3-4b75-bb37-3bcb87b0d27d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2879088906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2879088906
Directory	/workspace/5.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.319563443
Short name	T96
Test name
Test status
Simulation time	210169384 ps
CPU time	2.09 seconds
Started	Jul 19 04:36:52 PM PDT 24
Finished	Jul 19 04:37:16 PM PDT 24
Peak memory	214616 kb
Host	smart-53ecefec-4c11-42be-990d-554d58204148
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319563443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev _csr_mem_rw_with_rand_reset.319563443
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.591083082
Short name	T145
Test name
Test status
Simulation time	94875604 ps
CPU time	0.86 seconds
Started	Jul 19 04:36:52 PM PDT 24
Finished	Jul 19 04:37:15 PM PDT 24
Peak memory	206256 kb
Host	smart-4397e062-2f75-4c16-94f9-fe3a0b73eeb0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=591083082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.591083082
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.1327946041
Short name	T28
Test name
Test status
Simulation time	35388883 ps
CPU time	0.69 seconds
Started	Jul 19 04:37:07 PM PDT 24
Finished	Jul 19 04:37:24 PM PDT 24
Peak memory	206224 kb
Host	smart-ec87dae0-2f9a-4a7c-9e19-9434691ded2e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1327946041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1327946041
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4065516396
Short name	T115
Test name
Test status
Simulation time	107590680 ps
CPU time	1.09 seconds
Started	Jul 19 04:36:54 PM PDT 24
Finished	Jul 19 04:37:18 PM PDT 24
Peak memory	206368 kb
Host	smart-8ade3c35-8755-4bc5-a1dc-e4c6e7d7bef7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4065516396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.4065516396
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1446671835
Short name	T131
Test name
Test status
Simulation time	142122912 ps
CPU time	1.56 seconds
Started	Jul 19 04:36:56 PM PDT 24
Finished	Jul 19 04:37:19 PM PDT 24
Peak memory	206524 kb
Host	smart-ff4e035a-99ab-4434-aa9a-1055c4836dac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1446671835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1446671835
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2032589987
Short name	T64
Test name
Test status
Simulation time	333583902 ps
CPU time	2.35 seconds
Started	Jul 19 04:36:56 PM PDT 24
Finished	Jul 19 04:37:19 PM PDT 24
Peak memory	206396 kb
Host	smart-75be07a6-5326-42ef-af56-7127a615df89
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2032589987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2032589987
Directory	/workspace/6.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1838467253
Short name	T106
Test name
Test status
Simulation time	205278267 ps
CPU time	1.87 seconds
Started	Jul 19 04:36:54 PM PDT 24
Finished	Jul 19 04:37:18 PM PDT 24
Peak memory	214584 kb
Host	smart-69cffcac-1e8e-4b4c-bbff-a4fc67a9b7db
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838467253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde v_csr_mem_rw_with_rand_reset.1838467253
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3918758228
Short name	T171
Test name
Test status
Simulation time	52603891 ps
CPU time	0.87 seconds
Started	Jul 19 04:37:07 PM PDT 24
Finished	Jul 19 04:37:24 PM PDT 24
Peak memory	206244 kb
Host	smart-d08cd851-f077-4d7d-926c-c976e4ba0d1a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3918758228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3918758228
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.2167961891
Short name	T157
Test name
Test status
Simulation time	70161265 ps
CPU time	0.74 seconds
Started	Jul 19 04:36:57 PM PDT 24
Finished	Jul 19 04:37:18 PM PDT 24
Peak memory	206204 kb
Host	smart-99b89e02-c7d3-47f4-9d7d-a22e162d6483
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2167961891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2167961891
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1753181411
Short name	T159
Test name
Test status
Simulation time	464240126 ps
CPU time	2.22 seconds
Started	Jul 19 04:37:07 PM PDT 24
Finished	Jul 19 04:37:25 PM PDT 24
Peak memory	206420 kb
Host	smart-c23c4915-d711-40a8-9903-e921ae658730
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1753181411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1753181411
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.307803620
Short name	T152
Test name
Test status
Simulation time	175134057 ps
CPU time	1.76 seconds
Started	Jul 19 04:36:55 PM PDT 24
Finished	Jul 19 04:37:18 PM PDT 24
Peak memory	206440 kb
Host	smart-dbf8d795-617c-41d5-adb4-4fed87aea746
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=307803620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.307803620
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1193885415
Short name	T62
Test name
Test status
Simulation time	803733622 ps
CPU time	4.82 seconds
Started	Jul 19 04:36:55 PM PDT 24
Finished	Jul 19 04:37:21 PM PDT 24
Peak memory	206384 kb
Host	smart-17d624cb-e47a-4ed9-84a2-be20d2170cb7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1193885415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1193885415
Directory	/workspace/7.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3115356495
Short name	T109
Test name
Test status
Simulation time	198778377 ps
CPU time	1.92 seconds
Started	Jul 19 04:37:01 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	214664 kb
Host	smart-a9bf9e34-c55d-4c2b-abab-8bcea576523c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115356495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde v_csr_mem_rw_with_rand_reset.3115356495
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.48601203
Short name	T153
Test name
Test status
Simulation time	86840241 ps
CPU time	1.03 seconds
Started	Jul 19 04:37:01 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	206276 kb
Host	smart-f44b8e11-4d03-4ecb-a11d-794112031eed
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=48601203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.48601203
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.2343305636
Short name	T37
Test name
Test status
Simulation time	34778610 ps
CPU time	0.66 seconds
Started	Jul 19 04:36:58 PM PDT 24
Finished	Jul 19 04:37:18 PM PDT 24
Peak memory	206184 kb
Host	smart-1ada6970-d862-46f1-8a96-712503776e03
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2343305636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2343305636
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.551516406
Short name	T71
Test name
Test status
Simulation time	150916404 ps
CPU time	1.05 seconds
Started	Jul 19 04:36:54 PM PDT 24
Finished	Jul 19 04:37:17 PM PDT 24
Peak memory	206408 kb
Host	smart-47b9d9b7-881e-44ac-bc21-36627566850f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=551516406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.551516406
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2503237789
Short name	T117
Test name
Test status
Simulation time	262681532 ps
CPU time	3.15 seconds
Started	Jul 19 04:36:57 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	214684 kb
Host	smart-86c28086-9b8b-401d-a52a-b5e51f528a4c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2503237789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2503237789
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1062797705
Short name	T111
Test name
Test status
Simulation time	350791239 ps
CPU time	2.38 seconds
Started	Jul 19 04:36:58 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	206432 kb
Host	smart-2848770b-e3ac-470a-b5d1-9abf57b47108
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1062797705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1062797705
Directory	/workspace/8.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2409463671
Short name	T87
Test name
Test status
Simulation time	162405419 ps
CPU time	2.02 seconds
Started	Jul 19 04:36:59 PM PDT 24
Finished	Jul 19 04:37:21 PM PDT 24
Peak memory	214688 kb
Host	smart-cad7f7a0-6814-4dd3-881d-58c3cf8bb058
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409463671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde v_csr_mem_rw_with_rand_reset.2409463671
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3391843890
Short name	T30
Test name
Test status
Simulation time	85815890 ps
CPU time	1 seconds
Started	Jul 19 04:36:58 PM PDT 24
Finished	Jul 19 04:37:19 PM PDT 24
Peak memory	206300 kb
Host	smart-97c995a6-6ef8-4b1f-a401-1d5af8113baa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3391843890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3391843890
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.3997508187
Short name	T84
Test name
Test status
Simulation time	38923671 ps
CPU time	0.71 seconds
Started	Jul 19 04:37:04 PM PDT 24
Finished	Jul 19 04:37:21 PM PDT 24
Peak memory	206188 kb
Host	smart-34d04c4d-4967-4974-b2c0-3bb2daa4747f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3997508187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3997508187
Directory	/workspace/9.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.416140848
Short name	T4
Test name
Test status
Simulation time	209985096 ps
CPU time	1.53 seconds
Started	Jul 19 04:37:01 PM PDT 24
Finished	Jul 19 04:37:20 PM PDT 24
Peak memory	206488 kb
Host	smart-154d392e-4315-4130-b0df-e2085aad2624
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=416140848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.416140848
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2385313477
Short name	T138
Test name
Test status
Simulation time	74050208 ps
CPU time	1.65 seconds
Started	Jul 19 04:37:03 PM PDT 24
Finished	Jul 19 04:37:22 PM PDT 24
Peak memory	222348 kb
Host	smart-253f0d12-962a-4a7c-a59c-23914f219631
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2385313477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2385313477
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1254580752
Short name	T65
Test name
Test status
Simulation time	436959656 ps
CPU time	2.55 seconds
Started	Jul 19 04:37:04 PM PDT 24
Finished	Jul 19 04:37:23 PM PDT 24
Peak memory	206624 kb
Host	smart-b39e4e80-a8a7-4e5f-b27a-d772cdcabfb3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1254580752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1254580752
Directory	/workspace/9.usbdev_tl_intg_err/latest