Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	374	1		T3	8		T13	5		T5	5
all_pins[1]	374	1		T3	8		T13	5		T5	5
all_pins[2]	374	1		T3	8		T13	5		T5	5
all_pins[3]	374	1		T3	8		T13	5		T5	5
all_pins[4]	374	1		T3	8		T13	5		T5	5
all_pins[5]	374	1		T3	8		T13	5		T5	5
all_pins[6]	374	1		T3	8		T13	5		T5	5
all_pins[7]	374	1		T3	8		T13	5		T5	5
all_pins[8]	374	1		T3	8		T13	5		T5	5
all_pins[9]	374	1		T3	8		T13	5		T5	5
all_pins[10]	374	1		T3	8		T13	5		T5	5
all_pins[11]	374	1		T3	8		T13	5		T5	5
all_pins[12]	374	1		T3	8		T13	5		T5	5
all_pins[13]	374	1		T3	8		T13	5		T5	5
all_pins[14]	374	1		T3	8		T13	5		T5	5
all_pins[15]	374	1		T3	8		T13	5		T5	5
all_pins[16]	374	1		T3	8		T13	5		T5	5
all_pins[17]	374	1		T3	8		T13	5		T5	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5597	1		T3	122		T13	72		T5	75
values[0x1]	1135	1		T3	22		T13	18		T5	15
transitions[0x0=>0x1]	868	1		T3	18		T13	15		T5	13
transitions[0x1=>0x0]	879	1		T3	18		T13	15		T5	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	315	1		T3	6		T13	5		T5	5
all_pins[0]	values[0x1]	59	1		T3	2		T12	2		T28	1
all_pins[0]	transitions[0x0=>0x1]	45	1		T3	1		T12	2		T28	1
all_pins[0]	transitions[0x1=>0x0]	51	1		T3	1		T5	1		T12	2
all_pins[1]	values[0x0]	309	1		T3	6		T13	5		T5	4
all_pins[1]	values[0x1]	65	1		T3	2		T5	1		T12	2
all_pins[1]	transitions[0x0=>0x1]	48	1		T3	2		T5	1		T14	2
all_pins[1]	transitions[0x1=>0x0]	46	1		T3	1		T13	1		T12	1
all_pins[2]	values[0x0]	311	1		T3	7		T13	4		T5	5
all_pins[2]	values[0x1]	63	1		T3	1		T13	1		T12	3
all_pins[2]	transitions[0x0=>0x1]	46	1		T3	1		T12	2		T35	1
all_pins[2]	transitions[0x1=>0x0]	55	1		T13	3		T5	3		T12	1
all_pins[3]	values[0x0]	302	1		T3	8		T13	1		T5	2
all_pins[3]	values[0x1]	72	1		T13	4		T5	3		T12	2
all_pins[3]	transitions[0x0=>0x1]	57	1		T13	4		T5	3		T12	1
all_pins[3]	transitions[0x1=>0x0]	38	1		T12	1		T15	2		T36	1
all_pins[4]	values[0x0]	321	1		T3	8		T13	5		T5	5
all_pins[4]	values[0x1]	53	1		T12	2		T15	2		T36	2
all_pins[4]	transitions[0x0=>0x1]	36	1		T12	2		T15	2		T36	1
all_pins[4]	transitions[0x1=>0x0]	48	1		T13	1		T5	2		T15	1
all_pins[5]	values[0x0]	309	1		T3	8		T13	4		T5	3
all_pins[5]	values[0x1]	65	1		T13	1		T5	2		T15	1
all_pins[5]	transitions[0x0=>0x1]	51	1		T5	2		T15	1		T28	2
all_pins[5]	transitions[0x1=>0x0]	57	1		T3	4		T13	2		T36	2
all_pins[6]	values[0x0]	303	1		T3	4		T13	2		T5	5
all_pins[6]	values[0x1]	71	1		T3	4		T13	3		T36	2
all_pins[6]	transitions[0x0=>0x1]	57	1		T3	3		T13	2		T36	1
all_pins[6]	transitions[0x1=>0x0]	44	1		T5	1		T12	3		T14	2
all_pins[7]	values[0x0]	316	1		T3	7		T13	4		T5	4
all_pins[7]	values[0x1]	58	1		T3	1		T13	1		T5	1
all_pins[7]	transitions[0x0=>0x1]	46	1		T3	1		T13	1		T5	1
all_pins[7]	transitions[0x1=>0x0]	44	1		T5	1		T12	1		T14	1
all_pins[8]	values[0x0]	318	1		T3	8		T13	5		T5	4
all_pins[8]	values[0x1]	56	1		T5	1		T12	2		T14	1
all_pins[8]	transitions[0x0=>0x1]	44	1		T5	1		T12	2		T14	1
all_pins[8]	transitions[0x1=>0x0]	45	1		T3	1		T13	3		T5	1
all_pins[9]	values[0x0]	317	1		T3	7		T13	2		T5	4
all_pins[9]	values[0x1]	57	1		T3	1		T13	3		T5	1
all_pins[9]	transitions[0x0=>0x1]	48	1		T13	3		T12	1		T15	2
all_pins[9]	transitions[0x1=>0x0]	62	1		T3	1		T12	1		T14	1
all_pins[10]	values[0x0]	303	1		T3	6		T13	5		T5	4
all_pins[10]	values[0x1]	71	1		T3	2		T5	1		T12	1
all_pins[10]	transitions[0x0=>0x1]	54	1		T3	2		T12	1		T14	1
all_pins[10]	transitions[0x1=>0x0]	44	1		T3	1		T13	1		T28	1
all_pins[11]	values[0x0]	313	1		T3	7		T13	4		T5	4
all_pins[11]	values[0x1]	61	1		T3	1		T13	1		T5	1
all_pins[11]	transitions[0x0=>0x1]	50	1		T3	1		T13	1		T5	1
all_pins[11]	transitions[0x1=>0x0]	48	1		T3	1		T13	3		T38	3
all_pins[12]	values[0x0]	315	1		T3	7		T13	2		T5	5
all_pins[12]	values[0x1]	59	1		T3	1		T13	3		T38	3
all_pins[12]	transitions[0x0=>0x1]	44	1		T3	1		T13	3		T38	3
all_pins[12]	transitions[0x1=>0x0]	51	1		T12	2		T15	1		T36	2
all_pins[13]	values[0x0]	308	1		T3	8		T13	5		T5	5
all_pins[13]	values[0x1]	66	1		T12	2		T15	1		T36	2
all_pins[13]	transitions[0x0=>0x1]	48	1		T12	2		T36	1		T37	1
all_pins[13]	transitions[0x1=>0x0]	50	1		T13	1		T5	2		T15	2
all_pins[14]	values[0x0]	306	1		T3	8		T13	4		T5	3
all_pins[14]	values[0x1]	68	1		T13	1		T5	2		T15	3
all_pins[14]	transitions[0x0=>0x1]	53	1		T13	1		T5	2		T15	3
all_pins[14]	transitions[0x1=>0x0]	54	1		T3	5		T5	2		T12	1
all_pins[15]	values[0x0]	305	1		T3	3		T13	5		T5	3
all_pins[15]	values[0x1]	69	1		T3	5		T5	2		T12	1
all_pins[15]	transitions[0x0=>0x1]	54	1		T3	5		T5	2		T15	1
all_pins[15]	transitions[0x1=>0x0]	55	1		T12	4		T14	2		T35	2
all_pins[16]	values[0x0]	304	1		T3	8		T13	5		T5	5
all_pins[16]	values[0x1]	70	1		T12	5		T14	2		T35	3
all_pins[16]	transitions[0x0=>0x1]	56	1		T12	5		T14	1		T35	3
all_pins[16]	transitions[0x1=>0x0]	38	1		T3	2		T14	1		T15	1
all_pins[17]	values[0x0]	322	1		T3	6		T13	5		T5	5
all_pins[17]	values[0x1]	52	1		T3	2		T14	2		T15	1
all_pins[17]	transitions[0x0=>0x1]	31	1		T3	1		T14	2		T15	1
all_pins[17]	transitions[0x1=>0x0]	49	1		T3	1		T12	2		T28	1