Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T3	7		T13	4		T5	4
all_values[1]	284	1		T3	7		T13	4		T5	4
all_values[2]	284	1		T3	7		T13	4		T5	4
all_values[3]	284	1		T3	7		T13	4		T5	4
all_values[4]	284	1		T3	7		T13	4		T5	4
all_values[5]	284	1		T3	7		T13	4		T5	4
all_values[6]	284	1		T3	7		T13	4		T5	4
all_values[7]	284	1		T3	7		T13	4		T5	4
all_values[8]	284	1		T3	7		T13	4		T5	4
all_values[9]	284	1		T3	7		T13	4		T5	4
all_values[10]	284	1		T3	7		T13	4		T5	4
all_values[11]	284	1		T3	7		T13	4		T5	4
all_values[12]	284	1		T3	7		T13	4		T5	4
all_values[13]	284	1		T3	7		T13	4		T5	4
all_values[14]	284	1		T3	7		T13	4		T5	4
all_values[15]	284	1		T3	7		T13	4		T5	4
all_values[16]	284	1		T3	7		T13	4		T5	4
all_values[17]	284	1		T3	7		T13	4		T5	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2827	1		T3	73		T13	36		T5	31
auto[1]	2285	1		T3	53		T13	36		T5	41

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	863	1		T3	21		T13	19		T5	23
auto[1]	4249	1		T3	105		T13	53		T5	49

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3008	1		T3	73		T13	46		T5	51
auto[1]	2104	1		T3	53		T13	26		T5	21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	14	1		T14	1		T53	1		T54	1
all_values[0]	auto[0]	auto[0]	auto[1]	70	1		T3	1		T13	1		T5	1
all_values[0]	auto[0]	auto[1]	auto[0]	16	1		T3	1		T13	2		T38	2
all_values[0]	auto[0]	auto[1]	auto[1]	53	1		T5	1		T12	3		T14	1
all_values[0]	auto[1]	auto[0]	auto[1]	75	1		T3	3		T13	1		T5	1
all_values[0]	auto[1]	auto[1]	auto[1]	56	1		T3	2		T5	1		T12	1
all_values[1]	auto[0]	auto[0]	auto[0]	24	1		T15	2		T35	1		T39	1
all_values[1]	auto[0]	auto[0]	auto[1]	46	1		T5	1		T12	1		T14	1
all_values[1]	auto[0]	auto[1]	auto[0]	18	1		T13	4		T15	2		T38	1
all_values[1]	auto[0]	auto[1]	auto[1]	70	1		T3	4		T12	3		T14	1
all_values[1]	auto[1]	auto[0]	auto[1]	66	1		T3	1		T5	1		T12	2
all_values[1]	auto[1]	auto[1]	auto[1]	60	1		T3	2		T5	2		T12	1
all_values[2]	auto[0]	auto[0]	auto[0]	30	1		T14	3		T15	2		T35	2
all_values[2]	auto[0]	auto[0]	auto[1]	59	1		T3	2		T13	1		T5	1
all_values[2]	auto[0]	auto[1]	auto[0]	25	1		T3	1		T13	1		T5	2
all_values[2]	auto[0]	auto[1]	auto[1]	60	1		T12	3		T35	1		T36	1
all_values[2]	auto[1]	auto[0]	auto[1]	67	1		T3	1		T13	1		T12	1
all_values[2]	auto[1]	auto[1]	auto[1]	43	1		T3	3		T13	1		T5	1
all_values[3]	auto[0]	auto[0]	auto[0]	38	1		T14	1		T15	3		T28	2
all_values[3]	auto[0]	auto[0]	auto[1]	50	1		T3	3		T35	2		T36	2
all_values[3]	auto[0]	auto[1]	auto[0]	17	1		T15	1		T38	1		T55	2
all_values[3]	auto[0]	auto[1]	auto[1]	56	1		T13	1		T5	3		T12	2
all_values[3]	auto[1]	auto[0]	auto[1]	75	1		T3	4		T5	1		T12	1
all_values[3]	auto[1]	auto[1]	auto[1]	48	1		T13	3		T12	4		T14	2
all_values[4]	auto[0]	auto[0]	auto[0]	32	1		T13	2		T5	2		T14	2
all_values[4]	auto[0]	auto[0]	auto[1]	56	1		T3	4		T12	2		T28	1
all_values[4]	auto[0]	auto[1]	auto[0]	22	1		T3	1		T13	2		T5	2
all_values[4]	auto[0]	auto[1]	auto[1]	55	1		T14	1		T15	1		T28	2
all_values[4]	auto[1]	auto[0]	auto[1]	63	1		T3	2		T12	2		T14	1
all_values[4]	auto[1]	auto[1]	auto[1]	56	1		T12	3		T15	2		T35	1
all_values[5]	auto[0]	auto[0]	auto[0]	37	1		T3	1		T12	2		T14	1
all_values[5]	auto[0]	auto[0]	auto[1]	70	1		T3	2		T13	2		T5	1
all_values[5]	auto[0]	auto[1]	auto[0]	17	1		T13	1		T12	1		T28	1
all_values[5]	auto[0]	auto[1]	auto[1]	43	1		T3	1		T5	1		T12	2
all_values[5]	auto[1]	auto[0]	auto[1]	61	1		T3	3		T12	1		T15	1
all_values[5]	auto[1]	auto[1]	auto[1]	56	1		T13	1		T5	2		T14	1
all_values[6]	auto[0]	auto[0]	auto[0]	30	1		T15	4		T28	4		T35	1
all_values[6]	auto[0]	auto[0]	auto[1]	59	1		T3	1		T5	2		T12	3
all_values[6]	auto[0]	auto[1]	auto[0]	23	1		T3	1		T13	1		T5	1
all_values[6]	auto[0]	auto[1]	auto[1]	54	1		T3	3		T13	1		T14	1
all_values[6]	auto[1]	auto[0]	auto[1]	70	1		T5	1		T12	3		T14	1
all_values[6]	auto[1]	auto[1]	auto[1]	48	1		T3	2		T13	2		T12	1
all_values[7]	auto[0]	auto[0]	auto[0]	26	1		T13	1		T5	2		T12	1
all_values[7]	auto[0]	auto[0]	auto[1]	63	1		T3	2		T14	1		T28	1
all_values[7]	auto[0]	auto[1]	auto[0]	23	1		T3	1		T15	1		T28	1
all_values[7]	auto[0]	auto[1]	auto[1]	51	1		T3	1		T13	2		T5	1
all_values[7]	auto[1]	auto[0]	auto[1]	69	1		T3	2		T13	1		T5	1
all_values[7]	auto[1]	auto[1]	auto[1]	52	1		T3	1		T12	2		T15	1
all_values[8]	auto[0]	auto[0]	auto[0]	24	1		T14	1		T28	1		T35	1
all_values[8]	auto[0]	auto[0]	auto[1]	68	1		T3	2		T13	1		T5	1
all_values[8]	auto[0]	auto[1]	auto[0]	14	1		T13	1		T12	1		T35	1
all_values[8]	auto[0]	auto[1]	auto[1]	66	1		T3	1		T5	2		T12	3
all_values[8]	auto[1]	auto[0]	auto[1]	62	1		T3	3		T13	1		T15	1
all_values[8]	auto[1]	auto[1]	auto[1]	50	1		T3	1		T13	1		T5	1
all_values[9]	auto[0]	auto[0]	auto[0]	34	1		T14	1		T15	1		T28	1
all_values[9]	auto[0]	auto[0]	auto[1]	72	1		T3	3		T12	1		T28	2
all_values[9]	auto[0]	auto[1]	auto[0]	13	1		T13	1		T12	1		T14	1
all_values[9]	auto[0]	auto[1]	auto[1]	52	1		T13	1		T5	1		T12	4
all_values[9]	auto[1]	auto[0]	auto[1]	56	1		T3	1		T5	1		T35	2
all_values[9]	auto[1]	auto[1]	auto[1]	57	1		T3	3		T13	2		T5	2
all_values[10]	auto[0]	auto[0]	auto[0]	36	1		T3	3		T12	1		T14	1
all_values[10]	auto[0]	auto[0]	auto[1]	66	1		T3	1		T13	2		T12	1
all_values[10]	auto[0]	auto[1]	auto[0]	25	1		T13	1		T5	1		T39	3
all_values[10]	auto[0]	auto[1]	auto[1]	55	1		T3	1		T5	2		T12	1
all_values[10]	auto[1]	auto[0]	auto[1]	44	1		T12	3		T15	1		T28	1
all_values[10]	auto[1]	auto[1]	auto[1]	58	1		T3	2		T13	1		T5	1
all_values[11]	auto[0]	auto[0]	auto[0]	24	1		T3	1		T5	1		T14	1
all_values[11]	auto[0]	auto[0]	auto[1]	60	1		T3	3		T13	2		T12	1
all_values[11]	auto[0]	auto[1]	auto[0]	8	1		T38	2		T55	1		T53	1
all_values[11]	auto[0]	auto[1]	auto[1]	57	1		T13	1		T5	2		T12	3
all_values[11]	auto[1]	auto[0]	auto[1]	77	1		T12	2		T14	2		T15	2
all_values[11]	auto[1]	auto[1]	auto[1]	58	1		T3	3		T13	1		T5	1
all_values[12]	auto[0]	auto[0]	auto[0]	42	1		T5	3		T14	1		T15	1
all_values[12]	auto[0]	auto[0]	auto[1]	62	1		T3	3		T12	3		T14	1
all_values[12]	auto[0]	auto[1]	auto[0]	27	1		T13	1		T5	1		T12	1
all_values[12]	auto[0]	auto[1]	auto[1]	63	1		T13	2		T12	2		T15	2
all_values[12]	auto[1]	auto[0]	auto[1]	56	1		T3	3		T15	1		T28	2
all_values[12]	auto[1]	auto[1]	auto[1]	34	1		T3	1		T13	1		T12	1
all_values[13]	auto[0]	auto[0]	auto[0]	26	1		T3	3		T14	1		T15	1
all_values[13]	auto[0]	auto[0]	auto[1]	71	1		T3	1		T13	2		T5	1
all_values[13]	auto[0]	auto[1]	auto[0]	9	1		T3	1		T36	1		T39	1
all_values[13]	auto[0]	auto[1]	auto[1]	51	1		T5	2		T12	2		T35	1
all_values[13]	auto[1]	auto[0]	auto[1]	73	1		T3	1		T13	2		T5	1
all_values[13]	auto[1]	auto[1]	auto[1]	54	1		T3	1		T12	3		T35	1
all_values[14]	auto[0]	auto[0]	auto[0]	30	1		T12	1		T14	1		T15	1
all_values[14]	auto[0]	auto[0]	auto[1]	72	1		T3	3		T13	2		T5	1
all_values[14]	auto[0]	auto[1]	auto[0]	13	1		T14	3		T38	1		T39	2
all_values[14]	auto[0]	auto[1]	auto[1]	54	1		T3	2		T5	2		T15	2
all_values[14]	auto[1]	auto[0]	auto[1]	60	1		T3	2		T13	2		T12	2
all_values[14]	auto[1]	auto[1]	auto[1]	55	1		T5	1		T15	1		T28	1
all_values[15]	auto[0]	auto[0]	auto[0]	21	1		T5	2		T36	1		T38	1
all_values[15]	auto[0]	auto[0]	auto[1]	65	1		T3	1		T13	2		T12	1
all_values[15]	auto[0]	auto[1]	auto[0]	16	1		T3	1		T36	3		T38	1
all_values[15]	auto[0]	auto[1]	auto[1]	72	1		T3	2		T5	1		T12	2
all_values[15]	auto[1]	auto[0]	auto[1]	68	1		T3	1		T13	2		T5	1
all_values[15]	auto[1]	auto[1]	auto[1]	42	1		T3	2		T15	1		T35	1
all_values[16]	auto[0]	auto[0]	auto[0]	37	1		T3	3		T13	1		T14	1
all_values[16]	auto[0]	auto[0]	auto[1]	52	1		T3	1		T13	2		T15	1
all_values[16]	auto[0]	auto[1]	auto[0]	21	1		T3	1		T5	4		T12	1
all_values[16]	auto[0]	auto[1]	auto[1]	52	1		T3	1		T12	1		T14	1
all_values[16]	auto[1]	auto[0]	auto[1]	71	1		T3	1		T13	1		T12	2
all_values[16]	auto[1]	auto[1]	auto[1]	51	1		T12	3		T35	2		T36	2
all_values[17]	auto[0]	auto[0]	auto[0]	26	1		T3	1		T5	2		T14	1
all_values[17]	auto[0]	auto[0]	auto[1]	60	1		T13	2		T5	1		T12	2
all_values[17]	auto[0]	auto[1]	auto[0]	25	1		T3	1		T28	3		T39	1
all_values[17]	auto[0]	auto[1]	auto[1]	60	1		T3	3		T12	2		T14	1
all_values[17]	auto[1]	auto[0]	auto[1]	62	1		T13	2		T5	1		T12	3
all_values[17]	auto[1]	auto[1]	auto[1]	51	1		T3	2		T14	2		T36	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal