e971cd9798| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | usbdev_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | usbdev_csr_hw_reset | 0.910s | 71.275us | 5 | 5 | 100.00 |
| V1 | csr_rw | usbdev_csr_rw | 1.090s | 138.681us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | usbdev_csr_bit_bash | 9.010s | 1.735ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | usbdev_csr_aliasing | 3.450s | 366.030us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | usbdev_csr_mem_rw_with_rand_reset | 2.950s | 121.636us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | usbdev_csr_rw | 1.090s | 138.681us | 20 | 20 | 100.00 |
| usbdev_csr_aliasing | 3.450s | 366.030us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | usbdev_mem_walk | 4.800s | 733.595us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | usbdev_mem_partial_access | 2.430s | 253.506us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | in_trans | usbdev_in_trans | 0 | 50 | 0.00 | ||
| V2 | data_toggle_clear | usbdev_data_toggle_clear | 0 | 50 | 0.00 | ||
| V2 | phy_pins_sense | usbdev_phy_pins_sense | 0 | 50 | 0.00 | ||
| V2 | av_buffer | usbdev_av_buffer | 0 | 50 | 0.00 | ||
| V2 | rx_fifo | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | phy_config_tx_osc_test_mode | usbdev_phy_config_tx_osc_test_mode | 0 | 1 | 0.00 | ||
| V2 | phy_config_eop_single_bit_handling | usbdev_phy_config_eop_single_bit_handling | 0 | 1 | 0.00 | ||
| V2 | phy_config_pinflip | usbdev_phy_config_pinflip | 0 | 50 | 0.00 | ||
| V2 | phy_config_rand_bus_type | usbdev_phy_config_rand_bus_type | 0 | 5 | 0.00 | ||
| V2 | phy_config_rx_dp_dn | usbdev_phy_config_rx_dp_dn | 0 | 1 | 0.00 | ||
| V2 | phy_config_tx_use_d_se0 | usbdev_phy_config_tx_use_d_se0 | 0 | 1 | 0.00 | ||
| V2 | phy_config_usb_ref_disable | usbdev_phy_config_usb_ref_disable | 0 | 50 | 0.00 | ||
| V2 | max_length_out_transaction | usbdev_max_length_out_transaction | 0 | 50 | 0.00 | ||
| usbdev_stream_len_max | 0 | 50 | 0.00 | ||||
| V2 | max_length_in_transaction | usbdev_max_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_out_transaction | usbdev_min_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_in_transaction | usbdev_min_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | random_length_out_transaction | usbdev_random_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | random_length_in_transaction | usbdev_random_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | out_stall | usbdev_out_stall | 0 | 50 | 0.00 | ||
| V2 | in_stall | usbdev_in_stall | 0 | 50 | 0.00 | ||
| V2 | out_iso | usbdev_out_iso | 0 | 50 | 0.00 | ||
| V2 | in_iso | usbdev_in_iso | 0 | 50 | 0.00 | ||
| V2 | pkt_received | usbdev_pkt_received | 0 | 50 | 0.00 | ||
| V2 | pkt_sent | usbdev_pkt_sent | 0 | 50 | 0.00 | ||
| V2 | disconnected | usbdev_disconnected | 0 | 50 | 0.00 | ||
| V2 | host_lost | usbdev_host_lost | 0 | 1 | 0.00 | ||
| V2 | link_reset | usbdev_link_reset | 0 | 1 | 0.00 | ||
| V2 | link_suspend | usbdev_link_suspend | 0 | 50 | 0.00 | ||
| V2 | link_resume | usbdev_link_resume | 0 | 50 | 0.00 | ||
| V2 | av_empty | usbdev_av_empty | 0 | 5 | 0.00 | ||
| V2 | rx_full | usbdev_rx_full | 0 | 1 | 0.00 | ||
| V2 | av_overflow | usbdev_av_overflow | 0 | 5 | 0.00 | ||
| V2 | link_in_err | usbdev_link_in_err | 0 | 50 | 0.00 | ||
| V2 | rx_crc_err | usbdev_rx_crc_err | 0 | 50 | 0.00 | ||
| V2 | rx_pid_err | usbdev_rx_pid_err | 0 | 5 | 0.00 | ||
| V2 | rx_bitstuff_err | usbdev_bitstuff_err | 0 | 50 | 0.00 | ||
| V2 | link_out_err | usbdev_link_out_err | 0 | 1 | 0.00 | ||
| V2 | enable | usbdev_enable | 0 | 50 | 0.00 | ||
| V2 | resume_link_active | usbdev_resume_link_active | 0 | 1 | 0.00 | ||
| V2 | device_address | usbdev_device_address | 0 | 50 | 0.00 | ||
| V2 | invalid_data1_data0_toggle_test | usbdev_invalid_data1_data0_toggle_test | 0 | 1 | 0.00 | ||
| V2 | setup_stage | usbdev_setup_stage | 0 | 50 | 0.00 | ||
| V2 | endpoint_access | usbdev_endpoint_access | 0 | 50 | 0.00 | ||
| V2 | disable_endpoint | usbdev_disable_endpoint | 0 | 50 | 0.00 | ||
| V2 | out_trans_nak | usbdev_out_trans_nak | 0 | 50 | 0.00 | ||
| V2 | setup_trans_ignored | usbdev_setup_trans_ignored | 0 | 50 | 0.00 | ||
| V2 | nak_trans | usbdev_nak_trans | 0 | 50 | 0.00 | ||
| V2 | stall_trans | usbdev_stall_trans | 0 | 50 | 0.00 | ||
| V2 | setup_priority_over_stall_response | usbdev_setup_priority_over_stall_response | 0 | 5 | 0.00 | ||
| V2 | stall_priority_over_nak | usbdev_stall_priority_over_nak | 0 | 50 | 0.00 | ||
| V2 | pending_in_trans | usbdev_pending_in_trans | 0 | 50 | 0.00 | ||
| V2 | streaming_test | usbdev_streaming_out | 0 | 50 | 0.00 | ||
| V2 | max_clock_error_untracked | usbdev_freq_hiclk | 0 | 5 | 0.00 | ||
| usbdev_freq_loclk | 0 | 5 | 0.00 | ||||
| V2 | max_clock_error_tracking | usbdev_freq_hiclk_max | 0 | 5 | 0.00 | ||
| usbdev_freq_loclk_max | 0 | 5 | 0.00 | ||||
| V2 | max_phase_error | usbdev_freq_phase | 0 | 5 | 0.00 | ||
| V2 | min_inter_pkt_delay | usbdev_min_inter_pkt_delay | 0 | 50 | 0.00 | ||
| V2 | max_inter_pkt_delay | usbdev_max_inter_pkt_delay | 0 | 50 | 0.00 | ||
| V2 | device_timeout_missing_host_handshake | usbdev_timeout_missing_host_handshake | 0 | 50 | 0.00 | ||
| V2 | device_timeout | usbdev_device_timeout | 0 | 50 | 0.00 | ||
| V2 | packet_buffer | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | nak_to_out_trans_when_avbuffer_empty_rxfifo_full | usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full | 0 | 1 | 0.00 | ||
| V2 | aon_wake_resume | usbdev_aon_wake_resume | 0 | 50 | 0.00 | ||
| V2 | aon_wake_reset | usbdev_aon_wake_reset | 0 | 50 | 0.00 | ||
| V2 | aon_wake_disconnect | usbdev_aon_wake_disconnect | 0 | 50 | 0.00 | ||
| V2 | invalid_sync | usbdev_invalid_sync | 0 | 50 | 0.00 | ||
| V2 | spurious_pids_ignored | usbdev_spurious_pids_ignored | 0 | 50 | 0.00 | ||
| V2 | low_speed_traffic | usbdev_low_speed_traffic | 0 | 50 | 0.00 | ||
| V2 | rand_bus_resets | usbdev_rand_bus_resets | 0 | 10 | 0.00 | ||
| V2 | rand_disconnects | usbdev_rand_bus_disconnects | 0 | 10 | 0.00 | ||
| V2 | rand_suspends | usbdev_rand_suspends | 0 | 10 | 0.00 | ||
| V2 | max_usb_traffic | usbdev_max_usb_traffic | 0 | 50 | 0.00 | ||
| V2 | stress_usb_traffic | usbdev_stress_usb_traffic | 0 | 5 | 0.00 | ||
| V2 | in_packet_retraction | usbdev_iso_retraction | 0 | 50 | 0.00 | ||
| V2 | data_toggle_restore | usbdev_data_toggle_restore | 0 | 50 | 0.00 | ||
| V2 | setup_priority | usbdev_setup_priority | 0 | 5 | 0.00 | ||
| V2 | fifo_resets | usbdev_fifo_rst | 0 | 50 | 0.00 | ||
| V2 | intr_test | usbdev_intr_test | 0.780s | 52.537us | 50 | 50 | 100.00 |
| V2 | alert_test | usbdev_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | usbdev_tl_errors | 3.220s | 309.216us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | usbdev_tl_errors | 3.220s | 309.216us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | usbdev_csr_hw_reset | 0.910s | 71.275us | 5 | 5 | 100.00 |
| usbdev_csr_rw | 1.090s | 138.681us | 20 | 20 | 100.00 | ||
| usbdev_csr_aliasing | 3.450s | 366.030us | 5 | 5 | 100.00 | ||
| usbdev_same_csr_outstanding | 2.260s | 400.486us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | usbdev_csr_hw_reset | 0.910s | 71.275us | 5 | 5 | 100.00 |
| usbdev_csr_rw | 1.090s | 138.681us | 20 | 20 | 100.00 | ||
| usbdev_csr_aliasing | 3.450s | 366.030us | 5 | 5 | 100.00 | ||
| usbdev_same_csr_outstanding | 2.260s | 400.486us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 2841 | 3.17 | |||
| V2S | tl_intg_err | usbdev_sec_cm | 0 | 5 | 0.00 | ||
| usbdev_tl_intg_err | 6.200s | 1.954ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | usbdev_tl_intg_err | 6.200s | 1.954ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | dpi_config_host | usbdev_dpi_config_host | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | usbdev_stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| usbdev_stress_all | 0 | 50 | 0.00 | ||||
| TOTAL | 175 | 3042 | 5.75 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 82 | 82 | 3 | 3.66 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 67.77 | 65.51 | 59.58 | 85.50 | 0.00 | 69.84 | 97.77 | 96.22 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 1434 failures:
0.usbdev_aon_wake_disconnect.10132642010776154145912353005956354705525879929237361790988458163261211264865
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_disconnect/latest/run.log
1.usbdev_aon_wake_disconnect.6602182673292573764400797245975441792998854406752021950753698638993702065095
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_aon_wake_disconnect/latest/run.log
... and 26 more failures.
0.usbdev_aon_wake_resume.18603868900169741317908234171316493257864701626925464420211445017958305603907
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_resume/latest/run.log
1.usbdev_aon_wake_resume.69517479536670636184293350614802917528240712000212673547253764855612895891697
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_aon_wake_resume/latest/run.log
... and 26 more failures.
0.usbdev_av_empty.70946405499129853809539901402556127391764580741646929866724918298296073036212
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_empty/latest/run.log
1.usbdev_av_empty.109318845756018414733200707594165717813385899790805711165347382463221246864578
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_empty/latest/run.log
... and 3 more failures.
0.usbdev_bitstuff_err.61241851906616889083637148662728738830693078835754791476546874219885817257318
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_bitstuff_err/latest/run.log
1.usbdev_bitstuff_err.113589350699627538479105048808301579505964132942740350832730290875052808328848
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_bitstuff_err/latest/run.log
... and 26 more failures.
0.usbdev_data_toggle_restore.29982111539083075874952610805889856473921429998935673510931883898257979930565
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_restore/latest/run.log
1.usbdev_data_toggle_restore.41942533591063829161021437020245392115706875609490717769653774987665211131062
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_data_toggle_restore/latest/run.log
... and 26 more failures.
Job killed most likely because its dependent job failed. has 1433 failures:
0.usbdev_aon_wake_reset.77495328997072653452596952423099796622882768050388773364978326367988579764973
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_reset/latest/run.log
1.usbdev_aon_wake_reset.92412431573283220639561260451392305956666974025982745125723382599608693329973
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_aon_wake_reset/latest/run.log
... and 26 more failures.
0.usbdev_av_buffer.99572338204608846082654966901904909763094352468864577250740519387538191353944
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_buffer/latest/run.log
1.usbdev_av_buffer.90251625655385298094579362847747326707219810883796525030874443010016340715257
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_buffer/latest/run.log
... and 26 more failures.
0.usbdev_av_overflow.29559549278116688222443725511869201736883949548227518727685947124326443403013
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_overflow/latest/run.log
1.usbdev_av_overflow.5712856719717763941718809832110725313521337344027234391528385222103819530869
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_overflow/latest/run.log
... and 3 more failures.
0.usbdev_data_toggle_clear.105054766518851363198148124540874025186228894056732824480675362014487741427575
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_clear/latest/run.log
1.usbdev_data_toggle_clear.19347929113594650439677281993000171464433296320153426651981461814579253911298
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_data_toggle_clear/latest/run.log
... and 26 more failures.
0.usbdev_device_address.115025789901831489526122448838453642664804146645598108434951096322885350566057
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_device_address/latest/run.log
1.usbdev_device_address.112425942150236529957786341468050353071108058639883543161789635782842957777122
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_device_address/latest/run.log
... and 26 more failures.