Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15710342	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16472696	1		T1	5		T2	19		T3	9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31579977	1		T1	4		T2	18		T3	8
values[0x0]	301307	1		T1	4		T2	2		T3	4
values[0x1]	301754	1		T1	3		T2	5		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12528263	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19654775	1		T1	7		T2	21		T3	12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	100093	1		T1	1		T2	1		T7	3
valid_sources[0x01]	98185	1		T18	1		T5	595		T8	3
valid_sources[0x02]	98071	1		T2	1		T32	12		T35	2
valid_sources[0x03]	226000	1		T17	3		T5	609		T42	53
valid_sources[0x04]	98229	1		T17	1		T5	649		T99	1
valid_sources[0x05]	99567	1		T32	3		T7	2		T5	630
valid_sources[0x06]	182508	1		T5	576		T42	11		T150	84
valid_sources[0x07]	97542	1		T30	1		T32	1		T17	1
valid_sources[0x08]	100252	1		T31	1		T32	4		T17	1
valid_sources[0x09]	98583	1		T32	5		T7	2		T5	612
valid_sources[0x0a]	100067	1		T5	593		T55	1		T42	31
valid_sources[0x0b]	207291	1		T32	3		T5	550		T8	1
valid_sources[0x0c]	99553	1		T30	1		T5	626		T84	9
valid_sources[0x0d]	99158	1		T32	4		T17	1		T5	611
valid_sources[0x0e]	99747	1		T17	1		T5	626		T42	40
valid_sources[0x0f]	98507	1		T32	8		T5	595		T42	28
valid_sources[0x10]	421377	1		T18	1		T5	612		T42	3
valid_sources[0x11]	102529	1		T5	555		T84	18		T8	2
valid_sources[0x12]	171357	1		T2	1		T32	6		T17	1
valid_sources[0x13]	98498	1		T32	7		T7	3		T5	587
valid_sources[0x14]	119607	1		T5	625		T42	38		T150	114
valid_sources[0x15]	99161	1		T17	1		T5	599		T41	2
valid_sources[0x16]	98913	1		T32	1		T5	580		T42	125
valid_sources[0x17]	100169	1		T31	1		T32	4		T17	4
valid_sources[0x18]	275012	1		T32	1		T7	2		T5	671
valid_sources[0x19]	98004	1		T32	1		T5	614		T41	6
valid_sources[0x1a]	99485	1		T32	8		T7	2		T5	587
valid_sources[0x1b]	98331	1		T5	599		T42	16		T150	95
valid_sources[0x1c]	124425	1		T32	2		T17	1		T5	618
valid_sources[0x1d]	99608	1		T32	2		T5	579		T307	2
valid_sources[0x1e]	97429	1		T1	1		T32	1		T33	22
valid_sources[0x1f]	126470	1		T1	1		T30	1		T27	2710
valid_sources[0x20]	100362	1		T32	5		T5	658		T22	1
valid_sources[0x21]	123353	1		T32	3		T17	1		T5	630
valid_sources[0x22]	137153	1		T32	4		T17	1		T5	618
valid_sources[0x23]	98664	1		T2	1		T32	14		T5	605
valid_sources[0x24]	98135	1		T7	1		T5	614		T149	1
valid_sources[0x25]	229310	1		T2	1		T34	1		T5	604
valid_sources[0x26]	98137	1		T32	4		T5	600		T42	21
valid_sources[0x27]	97702	1		T32	1		T5	646		T84	5
valid_sources[0x28]	98882	1		T18	2		T5	628		T55	1
valid_sources[0x29]	122121	1		T32	2		T34	8		T5	611
valid_sources[0x2a]	97614	1		T29	1		T17	2		T18	1
valid_sources[0x2b]	287186	1		T17	3		T5	609		T41	1
valid_sources[0x2c]	100294	1		T32	3		T5	578		T42	10
valid_sources[0x2d]	152643	1		T32	1		T5	593		T19	1
valid_sources[0x2e]	177519	1		T32	2		T34	1		T5	601
valid_sources[0x2f]	205832	1		T32	8		T7	1		T17	2
valid_sources[0x30]	101642	1		T32	4		T18	1		T5	636
valid_sources[0x31]	98723	1		T32	6		T17	1		T5	586
valid_sources[0x32]	97761	1		T32	4		T5	613		T42	66
valid_sources[0x33]	125391	1		T1	1		T30	2		T32	18
valid_sources[0x34]	100076	1		T17	2		T5	642		T175	1
valid_sources[0x35]	98473	1		T5	606		T20	2		T42	24
valid_sources[0x36]	99073	1		T32	2		T5	587		T42	84
valid_sources[0x37]	98619	1		T7	3		T18	1		T5	654
valid_sources[0x38]	98541	1		T7	1		T17	1		T5	623
valid_sources[0x39]	99540	1		T5	586		T42	1		T150	106
valid_sources[0x3a]	97458	1		T35	2		T7	1		T5	640
valid_sources[0x3b]	98126	1		T7	1		T17	1		T5	611
valid_sources[0x3c]	98577	1		T1	1		T31	2		T5	650
valid_sources[0x3d]	140821	1		T2	1		T17	1		T5	632
valid_sources[0x3e]	98520	1		T31	2		T32	3		T17	1
valid_sources[0x3f]	99101	1		T2	1		T32	5		T17	1
valid_sources[0x40]	97823	1		T32	6		T5	596		T8	1
valid_sources[0x41]	98789	1		T32	6		T5	618		T149	1
valid_sources[0x42]	142967	1		T29	1		T7	1		T5	646
valid_sources[0x43]	189252	1		T7	1		T17	1		T5	632
valid_sources[0x44]	98582	1		T31	1		T7	2		T5	627
valid_sources[0x45]	134273	1		T32	3		T17	1		T5	633
valid_sources[0x46]	98923	1		T2	2		T32	2		T5	611
valid_sources[0x47]	98754	1		T32	3		T5	633		T42	21
valid_sources[0x48]	181028	1		T32	1		T7	1		T17	2
valid_sources[0x49]	98755	1		T32	5		T17	1		T5	563
valid_sources[0x4a]	99934	1		T32	5		T17	1		T5	573
valid_sources[0x4b]	143766	1		T32	5		T5	645		T42	34
valid_sources[0x4c]	97653	1		T17	1		T5	600		T8	2
valid_sources[0x4d]	98480	1		T32	1		T5	591		T41	3
valid_sources[0x4e]	100582	1		T17	4		T5	609		T307	2
valid_sources[0x4f]	99448	1		T7	3		T17	1		T5	664
valid_sources[0x50]	106794	1		T29	2		T5	601		T149	1
valid_sources[0x51]	97922	1		T5	596		T42	8		T150	89
valid_sources[0x52]	99023	1		T5	582		T42	85		T150	100
valid_sources[0x53]	97836	1		T32	2		T29	1		T17	2
valid_sources[0x54]	243743	1		T17	4		T5	666		T84	8
valid_sources[0x55]	97503	1		T1	1		T7	1		T5	642
valid_sources[0x56]	198974	1		T1	1		T5	608		T42	53
valid_sources[0x57]	98970	1		T32	2		T17	1		T5	649
valid_sources[0x58]	99294	1		T32	16		T17	1		T18	1
valid_sources[0x59]	212114	1		T32	2		T7	3		T5	576
valid_sources[0x5a]	226389	1		T32	1		T7	2		T17	1
valid_sources[0x5b]	190357	1		T28	5395		T5	616		T42	93
valid_sources[0x5c]	99611	1		T32	2		T7	2		T17	1
valid_sources[0x5d]	99499	1		T30	1		T32	19		T5	635
valid_sources[0x5e]	99684	1		T32	4		T7	1		T17	1
valid_sources[0x5f]	97566	1		T31	1		T32	2		T5	596
valid_sources[0x60]	132123	1		T1	1		T2	1		T7	3
valid_sources[0x61]	98454	1		T17	1		T5	631		T84	9
valid_sources[0x62]	98340	1		T32	3		T18	1		T5	603
valid_sources[0x63]	99109	1		T5	615		T21	1		T8	7
valid_sources[0x64]	98357	1		T17	2		T5	593		T42	18
valid_sources[0x65]	238012	1		T32	5		T7	1		T17	3
valid_sources[0x66]	97962	1		T30	1		T5	667		T84	5
valid_sources[0x67]	98583	1		T32	1		T5	658		T42	97
valid_sources[0x68]	167929	1		T32	1		T7	2		T5	611
valid_sources[0x69]	104585	1		T32	1		T17	1		T5	609
valid_sources[0x6a]	98387	1		T32	3		T5	628		T41	1
valid_sources[0x6b]	100716	1		T2	2		T17	4		T5	626
valid_sources[0x6c]	101229	1		T17	2		T5	614		T42	121
valid_sources[0x6d]	99430	1		T7	3		T17	3		T5	602
valid_sources[0x6e]	138210	1		T17	1		T5	589		T84	13
valid_sources[0x6f]	98186	1		T31	1		T32	10		T5	614
valid_sources[0x70]	280654	1		T32	1		T5	619		T55	1
valid_sources[0x71]	99597	1		T31	1		T7	5		T17	3
valid_sources[0x72]	144746	1		T32	11		T5	642		T42	9
valid_sources[0x73]	99079	1		T32	8		T5	605		T42	46
valid_sources[0x74]	98910	1		T5	595		T42	99		T150	96
valid_sources[0x75]	98651	1		T30	2		T32	2		T7	1
valid_sources[0x76]	97534	1		T32	1		T5	591		T99	2
valid_sources[0x77]	452484	1		T32	3		T7	2		T5	645
valid_sources[0x78]	180278	1		T32	3		T17	3		T5	573
valid_sources[0x79]	99054	1		T32	1		T17	1		T5	623
valid_sources[0x7a]	99929	1		T32	10		T7	1		T17	1
valid_sources[0x7b]	99326	1		T30	1		T32	2		T5	613
valid_sources[0x7c]	188905	1		T2	1		T5	563		T22	1
valid_sources[0x7d]	98352	1		T32	1		T5	584		T55	1
valid_sources[0x7e]	99365	1		T32	2		T5	612		T307	1
valid_sources[0x7f]	98843	1		T32	3		T17	1		T5	623
valid_sources[0x80]	133581	1		T32	5		T17	3		T5	586

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15990277

1

T1

1

T2

15

T3

5

values[0x0]

all_enables

biggest_size

248814

1

T1

3

T2

2

T3

2

values[0x1]

all_enables

biggest_size

233605

1

T1

1

T2

2

T3

2