Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	15722856	1		T1	6		T2	6		T3	6
full_word	16473615	1		T1	5		T2	19		T3	9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32196181	1		T1	11		T2	25		T3	15
auto[TlIntgErrCmd]	92	1		T187	5		T213	4		T211	3
auto[TlIntgErrData]	93	1		T187	9		T213	2		T211	2
auto[TlIntgErrBoth]	105	1		T187	6		T213	4		T211	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31581606	1		T1	4		T2	18		T3	8
auto[1]	614865	1		T1	7		T2	7		T3	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15591053	1		T1	3		T2	3		T3	3
auto[TlIntgErrNone]	partial	auto[1]	131537	1		T1	3		T2	3		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	15990435	1		T1	1		T2	15		T3	5
auto[TlIntgErrNone]	full_word	auto[1]	483156	1		T1	4		T2	4		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	26	1		T213	2		T211	1		T283	2
auto[TlIntgErrCmd]	partial	auto[1]	61	1		T187	4		T213	2		T211	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T187	1		T211	1		T284	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T187	5		T211	1		T277	1
auto[TlIntgErrData]	partial	auto[1]	41	1		T187	3		T213	2		T211	1
auto[TlIntgErrData]	full_word	auto[0]	7	1		T280	1		T285	1		T286	2
auto[TlIntgErrData]	full_word	auto[1]	2	1		T187	1		T287	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T187	2		T213	2		T211	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T187	3		T213	2		T211	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T288	1		T289	1		T286	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T187	1		T284	1		T287	1