Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	498558271	10151	0	0
ep_in_enable_rd_A	498558271	2613	0	0
ep_out_enable_rd_A	498558271	2579	0	0
in_iso_rd_A	498558271	2726	0	0
intr_enable_rd_A	498558271	3861	0	0
out_iso_rd_A	498558271	2298	0	0
phy_config_rd_A	498558271	1501	0	0
phy_pins_drive_rd_A	498558271	2025	0	0
rxenable_setup_rd_A	498558271	2479	0	0
set_nak_out_rd_A	498558271	2757	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498558271	10151	0	0
T187	37771	6	0	0
T188	4732	21	0	0
T189	3885	5	0	0
T211	29101	3	0	0
T212	6711	309	0	0
T213	20075	2	0	0
T218	6050	611	0	0
T219	6701	358	0	0
T225	7701	16	0	0
T230	8078	18	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498558271	2613	0	0
T187	37771	259	0	0
T215	9977	22	0	0
T220	8531	78	0	0
T230	8078	52	0	0
T231	4890	4	0	0
T267	4863	57	0	0
T277	20595	150	0	0
T278	44124	191	0	0
T279	4281	9	0	0
T280	40364	290	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498558271	2579	0	0
T187	37771	257	0	0
T215	9977	13	0	0
T220	8531	46	0	0
T230	8078	31	0	0
T231	4890	10	0	0
T267	4863	61	0	0
T277	20595	152	0	0
T278	44124	176	0	0
T279	4281	41	0	0
T280	40364	215	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498558271	2726	0	0
T187	37771	230	0	0
T215	9977	26	0	0
T220	8531	18	0	0
T222	16661	3	0	0
T230	8078	7	0	0
T231	4890	3	0	0
T267	4863	3	0	0
T277	20595	185	0	0
T278	44124	325	0	0
T279	4281	43	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498558271	3861	0	0
T187	37771	459	0	0
T199	1670	26	0	0
T215	9977	31	0	0
T220	8531	76	0	0
T230	8078	7	0	0
T231	4890	87	0	0
T267	4863	4	0	0
T277	20595	121	0	0
T281	4389	17	0	0
T282	2617	20	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498558271	2298	0	0
T187	37771	215	0	0
T215	9977	14	0	0
T220	8531	65	0	0
T230	8078	55	0	0
T231	4890	49	0	0
T267	4863	35	0	0
T277	20595	141	0	0
T278	44124	210	0	0
T279	4281	57	0	0
T280	40364	205	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498558271	1501	0	0
T187	37771	72	0	0
T215	9977	46	0	0
T220	8531	34	0	0
T230	8078	2	0	0
T231	4890	6	0	0
T267	4863	23	0	0
T277	20595	60	0	0
T278	44124	174	0	0
T279	4281	36	0	0
T280	40364	139	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498558271	2025	0	0
T187	37771	200	0	0
T215	9977	13	0	0
T220	8531	48	0	0
T230	8078	10	0	0
T231	4890	35	0	0
T267	4863	24	0	0
T277	20595	56	0	0
T278	44124	230	0	0
T279	4281	24	0	0
T280	40364	314	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498558271	2479	0	0
T187	37771	284	0	0
T215	9977	33	0	0
T220	8531	17	0	0
T230	8078	3	0	0
T231	4890	8	0	0
T267	4863	24	0	0
T277	20595	211	0	0
T278	44124	242	0	0
T279	4281	116	0	0
T280	40364	184	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	498558271	2757	0	0
T187	37771	240	0	0
T215	9977	21	0	0
T220	8531	18	0	0
T230	8078	33	0	0
T231	4890	44	0	0
T267	4863	46	0	0
T277	20595	187	0	0
T278	44124	222	0	0
T279	4281	85	0	0
T280	40364	245	0	0