Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.gen_no_stubbed_memory.u_memory_1p.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.24 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
TOTAL7685.71
CONT_ASSIGN42100.00
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
CONT_ASSIGN5200
ALWAYS6366100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
42 0 1
52 unreachable
63 1 1
64 1 1
65 1 1
66 1 1
67 1 1
==> MISSING_ELSE
72 1 1
MISSING_ELSE


Branch Coverage for Module : prim_generic_ram_1p
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 63 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 63 if (req_i) -2-: 64 if (write_i)

Branches:
-1--2-StatusTests
1 1 Covered T2,T3,T30
1 0 Covered T2,T3,T30
0 - Covered T1,T2,T3


Assert Coverage for Module : prim_generic_ram_1p
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataBitsPerMaskCheck_A 2672 2672 0 0
gen_wmask[0].MaskCheck_A 496706215 1025188 0 0
gen_wmask[1].MaskCheck_A 496706215 1025188 0 0
gen_wmask[2].MaskCheck_A 496706215 1025188 0 0
gen_wmask[3].MaskCheck_A 496706215 1025188 0 0


DataBitsPerMaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2672 2672 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T27 1 1 0 0
T30 1 1 0 0
T31 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T35 1 1 0 0

gen_wmask[0].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 496706215 1025188 0 0
T2 10041 14 0 0
T3 8744 3 0 0
T4 0 441 0 0
T7 0 3 0 0
T17 0 64 0 0
T27 507200 579 0 0
T28 105389 1216 0 0
T29 0 1 0 0
T30 7912 5 0 0
T31 6973 0 0 0
T32 8765 0 0 0
T33 6781 0 0 0
T34 7733 0 0 0
T35 8923 1 0 0

gen_wmask[1].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 496706215 1025188 0 0
T2 10041 14 0 0
T3 8744 3 0 0
T4 0 441 0 0
T7 0 3 0 0
T17 0 64 0 0
T27 507200 579 0 0
T28 105389 1216 0 0
T29 0 1 0 0
T30 7912 5 0 0
T31 6973 0 0 0
T32 8765 0 0 0
T33 6781 0 0 0
T34 7733 0 0 0
T35 8923 1 0 0

gen_wmask[2].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 496706215 1025188 0 0
T2 10041 14 0 0
T3 8744 3 0 0
T4 0 441 0 0
T7 0 3 0 0
T17 0 64 0 0
T27 507200 579 0 0
T28 105389 1216 0 0
T29 0 1 0 0
T30 7912 5 0 0
T31 6973 0 0 0
T32 8765 0 0 0
T33 6781 0 0 0
T34 7733 0 0 0
T35 8923 1 0 0

gen_wmask[3].MaskCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 496706215 1025188 0 0
T2 10041 14 0 0
T3 8744 3 0 0
T4 0 441 0 0
T7 0 3 0 0
T17 0 64 0 0
T27 507200 579 0 0
T28 105389 1216 0 0
T29 0 1 0 0
T30 7912 5 0 0
T31 6973 0 0 0
T32 8765 0 0 0
T33 6781 0 0 0
T34 7733 0 0 0
T35 8923 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%