Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17135007	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	17950149	1		T1	13759		T2	15		T3	1163

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34444269	1		T1	26725		T2	39		T3	3080
values[0x0]	319735	1		T1	200		T2	6		T3	444
values[0x1]	321152	1		T1	229		T2	16		T3	473

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13664480	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	21420676	1		T1	16480		T2	29		T3	2132

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	96470	1		T16	1		T17	1		T19	3
valid_sources[0x01]	98662	1		T27	2		T20	5		T4	103
valid_sources[0x02]	256787	1		T17	1		T19	8		T20	2
valid_sources[0x03]	125441	1		T17	1		T21	1		T4	77
valid_sources[0x04]	98460	1		T20	2		T4	99		T5	95
valid_sources[0x05]	98610	1		T17	1		T4	100		T5	99
valid_sources[0x06]	101683	1		T27	1		T17	1		T19	17
valid_sources[0x07]	177359	1		T17	1		T19	7		T4	105
valid_sources[0x08]	99989	1		T20	1		T4	100		T5	102
valid_sources[0x09]	303027	1		T27	2		T17	1		T4	103
valid_sources[0x0a]	96191	1		T4	107		T5	86		T155	649
valid_sources[0x0b]	216992	1		T17	1		T23	1		T38	3
valid_sources[0x0c]	98802	1		T17	3		T4	78		T5	103
valid_sources[0x0d]	158566	1		T6	7		T20	6		T4	110
valid_sources[0x0e]	248066	1		T2	2		T20	3		T4	98
valid_sources[0x0f]	98360	1		T2	2		T19	2		T4	113
valid_sources[0x10]	141163	1		T17	1		T19	4		T20	3
valid_sources[0x11]	97578	1		T43	1		T4	97		T5	79
valid_sources[0x12]	101902	1		T2	1		T27	4		T17	1
valid_sources[0x13]	96206	1		T27	6		T6	6		T19	1
valid_sources[0x14]	97211	1		T20	6		T43	3		T4	106
valid_sources[0x15]	186519	1		T17	1		T18	1		T20	1
valid_sources[0x16]	98663	1		T20	3		T4	84		T5	89
valid_sources[0x17]	98953	1		T17	1		T20	6		T4	97
valid_sources[0x18]	121875	1		T2	3		T27	1		T17	1
valid_sources[0x19]	99147	1		T7	9		T17	1		T18	1
valid_sources[0x1a]	204552	1		T17	1		T4	87		T5	105
valid_sources[0x1b]	154417	1		T2	1		T27	6		T17	1
valid_sources[0x1c]	224632	1		T23	1		T4	122		T5	101
valid_sources[0x1d]	98200	1		T4	86		T5	90		T155	579
valid_sources[0x1e]	98424	1		T17	1		T4	92		T5	102
valid_sources[0x1f]	363904	1		T17	1		T19	1		T20	3
valid_sources[0x20]	113958	1		T17	1		T19	7		T20	1
valid_sources[0x21]	102908	1		T27	4		T43	3		T4	101
valid_sources[0x22]	123025	1		T2	1		T20	2		T38	4
valid_sources[0x23]	97747	1		T19	1		T4	90		T5	86
valid_sources[0x24]	123827	1		T17	2		T20	6		T4	87
valid_sources[0x25]	99132	1		T27	1		T17	1		T20	2
valid_sources[0x26]	123142	1		T1	27154		T19	2		T23	2
valid_sources[0x27]	96124	1		T27	2		T19	5		T20	1
valid_sources[0x28]	149470	1		T17	1		T20	1		T4	109
valid_sources[0x29]	98699	1		T27	4		T20	1		T4	101
valid_sources[0x2a]	101109	1		T17	1		T20	2		T4	94
valid_sources[0x2b]	96035	1		T17	3		T19	2		T20	3
valid_sources[0x2c]	146535	1		T6	1		T17	1		T20	8
valid_sources[0x2d]	97788	1		T2	1		T27	4		T7	1
valid_sources[0x2e]	99400	1		T7	6		T17	2		T19	3
valid_sources[0x2f]	329684	1		T17	2		T20	4		T4	91
valid_sources[0x30]	96978	1		T17	2		T20	2		T4	101
valid_sources[0x31]	99324	1		T2	1		T6	4		T4	95
valid_sources[0x32]	97347	1		T17	2		T20	2		T4	110
valid_sources[0x33]	210838	1		T19	3		T4	103		T5	104
valid_sources[0x34]	96481	1		T17	1		T19	2		T4	81
valid_sources[0x35]	117765	1		T17	3		T19	1		T20	5
valid_sources[0x36]	98788	1		T20	3		T38	1		T4	97
valid_sources[0x37]	197593	1		T27	3		T17	1		T4	111
valid_sources[0x38]	98426	1		T17	1		T19	6		T20	1
valid_sources[0x39]	97937	1		T18	4		T4	100		T5	102
valid_sources[0x3a]	102189	1		T2	1		T7	33		T19	3
valid_sources[0x3b]	97191	1		T27	2		T16	1		T18	1
valid_sources[0x3c]	97433	1		T19	1		T20	4		T4	110
valid_sources[0x3d]	96799	1		T27	3		T17	1		T19	1
valid_sources[0x3e]	97054	1		T27	1		T7	8		T17	1
valid_sources[0x3f]	117203	1		T17	1		T23	3		T4	95
valid_sources[0x40]	99001	1		T19	1		T20	1		T23	1
valid_sources[0x41]	96094	1		T17	3		T19	2		T20	1
valid_sources[0x42]	99516	1		T17	3		T19	2		T20	1
valid_sources[0x43]	323533	1		T2	1		T4	85		T5	112
valid_sources[0x44]	130763	1		T17	1		T20	1		T4	97
valid_sources[0x45]	97878	1		T2	2		T17	2		T20	2
valid_sources[0x46]	100154	1		T27	2		T20	3		T38	15
valid_sources[0x47]	98986	1		T17	1		T18	1		T23	1
valid_sources[0x48]	231447	1		T17	1		T23	1		T4	97
valid_sources[0x49]	124952	1		T17	1		T20	1		T4	103
valid_sources[0x4a]	99032	1		T17	1		T4	122		T5	106
valid_sources[0x4b]	118635	1		T20	1		T43	3		T4	97
valid_sources[0x4c]	97485	1		T17	1		T4	82		T5	96
valid_sources[0x4d]	97455	1		T27	1		T17	1		T20	1
valid_sources[0x4e]	97955	1		T7	24		T17	1		T38	6
valid_sources[0x4f]	121910	1		T27	1		T7	3		T19	3
valid_sources[0x50]	96881	1		T20	1		T4	112		T5	85
valid_sources[0x51]	97509	1		T16	1		T17	1		T20	1
valid_sources[0x52]	95809	1		T27	5		T17	3		T20	1
valid_sources[0x53]	96372	1		T20	3		T4	97		T5	100
valid_sources[0x54]	96744	1		T2	1		T17	1		T20	3
valid_sources[0x55]	98359	1		T7	4		T17	1		T20	1
valid_sources[0x56]	97717	1		T27	4		T16	1		T20	1
valid_sources[0x57]	194116	1		T2	1		T17	2		T4	89
valid_sources[0x58]	96823	1		T19	3		T20	2		T21	1
valid_sources[0x59]	96661	1		T7	7		T19	3		T4	111
valid_sources[0x5a]	164039	1		T27	5		T19	1		T20	11
valid_sources[0x5b]	99676	1		T27	2		T6	11		T17	2
valid_sources[0x5c]	102085	1		T2	1		T6	3		T7	11
valid_sources[0x5d]	96016	1		T27	2		T17	1		T19	3
valid_sources[0x5e]	97733	1		T17	1		T19	2		T20	1
valid_sources[0x5f]	152856	1		T7	56		T20	1		T4	135
valid_sources[0x60]	99029	1		T7	10		T19	2		T4	108
valid_sources[0x61]	226609	1		T17	3		T20	1		T23	1
valid_sources[0x62]	97599	1		T17	1		T4	87		T5	114
valid_sources[0x63]	98296	1		T2	2		T17	1		T20	1
valid_sources[0x64]	191108	1		T27	4		T16	1		T17	3
valid_sources[0x65]	265649	1		T3	3997		T6	1		T17	1
valid_sources[0x66]	97975	1		T17	1		T20	2		T38	4
valid_sources[0x67]	109845	1		T17	1		T43	3		T4	94
valid_sources[0x68]	125072	1		T2	1		T27	2		T20	1
valid_sources[0x69]	420527	1		T27	4		T17	1		T20	3
valid_sources[0x6a]	428524	1		T19	6		T20	4		T38	2
valid_sources[0x6b]	144857	1		T27	5		T4	102		T5	90
valid_sources[0x6c]	117877	1		T20	1		T4	91		T5	105
valid_sources[0x6d]	98498	1		T2	1		T18	1		T20	4
valid_sources[0x6e]	116044	1		T4	107		T5	111		T155	696
valid_sources[0x6f]	213826	1		T20	2		T4	91		T5	102
valid_sources[0x70]	111968	1		T2	1		T17	1		T18	1
valid_sources[0x71]	97627	1		T4	111		T5	95		T155	523
valid_sources[0x72]	98120	1		T6	7		T7	11		T20	3
valid_sources[0x73]	97355	1		T17	1		T23	3		T4	112
valid_sources[0x74]	96211	1		T27	2		T4	91		T223	3
valid_sources[0x75]	101300	1		T27	3		T17	2		T19	3
valid_sources[0x76]	97187	1		T17	3		T4	128		T5	88
valid_sources[0x77]	187986	1		T16	1		T4	107		T5	94
valid_sources[0x78]	343683	1		T17	1		T20	2		T4	106
valid_sources[0x79]	315344	1		T6	3		T17	1		T4	122
valid_sources[0x7a]	118687	1		T7	7		T20	1		T4	93
valid_sources[0x7b]	143071	1		T17	1		T19	3		T20	2
valid_sources[0x7c]	96514	1		T27	10		T17	1		T4	101
valid_sources[0x7d]	95953	1		T2	3		T17	2		T19	1
valid_sources[0x7e]	96591	1		T2	1		T27	4		T17	1
valid_sources[0x7f]	97468	1		T2	1		T27	15		T20	3
valid_sources[0x80]	96386	1		T2	1		T17	2		T20	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17435246

1

T1

13455

T2

3

T3

292

values[0x0]

all_enables

biggest_size

264914

1

T1

144

T2

4

T3

427

values[0x1]

all_enables

biggest_size

249989

1

T1

160

T2

8

T3

444