Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	17149733	1		T1	13395		T2	46		T3	2834
full_word	17951109	1		T1	13759		T2	15		T3	1163

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35100582	1		T1	27154		T2	61		T3	3997
auto[TlIntgErrCmd]	96	1		T189	3		T190	6		T191	3
auto[TlIntgErrData]	87	1		T189	5		T190	2		T191	6
auto[TlIntgErrBoth]	77	1		T189	12		T190	2		T191	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	34446087	1		T1	26725		T2	39		T3	3080
auto[1]	654755	1		T1	429		T2	22		T3	917

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17010544	1		T1	13270		T2	36		T3	2788
auto[TlIntgErrNone]	partial	auto[1]	138944	1		T1	125		T2	10		T3	46
auto[TlIntgErrNone]	full_word	auto[0]	17435433	1		T1	13455		T2	3		T3	292
auto[TlIntgErrNone]	full_word	auto[1]	515661	1		T1	304		T2	12		T3	871
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T190	3		T191	2		T237	2
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T189	3		T190	3		T191	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T291	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T292	1		T288	1		T233	1
auto[TlIntgErrData]	partial	auto[0]	38	1		T189	1		T190	2		T191	4
auto[TlIntgErrData]	partial	auto[1]	42	1		T189	3		T191	2		T237	5
auto[TlIntgErrData]	full_word	auto[0]	4	1		T237	2		T268	1		T233	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T189	1		T237	1		T289	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T189	5		T190	1		T237	2
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T189	7		T190	1		T191	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T293	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T270	1		-	-		-	-