Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	506986973	12018	0	0
ep_in_enable_rd_A	506986973	3349	0	0
ep_out_enable_rd_A	506986973	3328	0	0
in_iso_rd_A	506986973	3687	0	0
intr_enable_rd_A	506986973	4685	0	0
out_iso_rd_A	506986973	3532	0	0
phy_config_rd_A	506986973	2040	0	0
phy_pins_drive_rd_A	506986973	2625	0	0
rxenable_setup_rd_A	506986973	2908	0	0
set_nak_out_rd_A	506986973	3016	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506986973	12018	0	0
T189	64587	5	0	0
T190	14456	5	0	0
T191	16150	2	0	0
T215	6314	820	0	0
T216	11127	19	0	0
T217	9708	16	0	0
T221	2807	291	0	0
T231	7944	22	0	0
T237	39947	9	0	0
T268	15664	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506986973	3349	0	0
T216	11127	36	0	0
T217	9708	69	0	0
T226	7521	54	0	0
T236	6038	46	0	0
T237	39947	465	0	0
T248	3961	34	0	0
T251	4196	4	0	0
T269	20784	395	0	0
T270	30807	128	0	0
T271	9188	5	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506986973	3328	0	0
T216	11127	87	0	0
T217	9708	88	0	0
T226	7521	63	0	0
T236	6038	49	0	0
T237	39947	324	0	0
T248	3961	79	0	0
T264	9606	37	0	0
T269	20784	273	0	0
T270	30807	180	0	0
T271	9188	15	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506986973	3687	0	0
T216	11127	10	0	0
T217	9708	56	0	0
T226	7521	109	0	0
T236	6038	52	0	0
T237	39947	590	0	0
T248	3961	36	0	0
T264	9606	22	0	0
T269	20784	191	0	0
T270	30807	154	0	0
T271	9188	33	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506986973	4685	0	0
T201	2909	20	0	0
T216	11127	156	0	0
T217	9708	144	0	0
T226	7521	11	0	0
T236	6038	6	0	0
T237	39947	583	0	0
T248	3961	3	0	0
T269	20784	321	0	0
T270	30807	146	0	0
T272	2020	5	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506986973	3532	0	0
T216	11127	98	0	0
T217	9708	19	0	0
T226	7521	23	0	0
T236	6038	72	0	0
T237	39947	531	0	0
T248	3961	69	0	0
T264	9606	13	0	0
T269	20784	225	0	0
T270	30807	90	0	0
T271	9188	72	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506986973	2040	0	0
T216	11127	37	0	0
T217	9708	32	0	0
T226	7521	29	0	0
T236	6038	6	0	0
T237	39947	281	0	0
T248	3961	22	0	0
T264	9606	24	0	0
T269	20784	153	0	0
T270	30807	89	0	0
T271	9188	14	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506986973	2625	0	0
T216	11127	86	0	0
T217	9708	42	0	0
T226	7521	55	0	0
T237	39947	463	0	0
T248	3961	16	0	0
T251	4196	21	0	0
T264	9606	29	0	0
T269	20784	160	0	0
T270	30807	63	0	0
T271	9188	7	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506986973	2908	0	0
T216	11127	50	0	0
T217	9708	56	0	0
T226	7521	120	0	0
T236	6038	8	0	0
T237	39947	424	0	0
T248	3961	25	0	0
T264	9606	16	0	0
T269	20784	299	0	0
T270	30807	109	0	0
T271	9188	34	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506986973	3016	0	0
T216	11127	62	0	0
T217	9708	49	0	0
T226	7521	47	0	0
T236	6038	58	0	0
T237	39947	302	0	0
T248	3961	98	0	0
T264	9606	12	0	0
T269	20784	269	0	0
T270	30807	73	0	0
T271	9188	29	0	0