Line Coverage for Module :
tlul_adapter_reg
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 91 | 1 | 1 | 100.00 |
ALWAYS | 95 | 6 | 6 | 100.00 |
ALWAYS | 101 | 8 | 8 | 100.00 |
ALWAYS | 141 | 6 | 6 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 154 | 1 | 1 | 100.00 |
CONT_ASSIGN | 204 | 1 | 1 | 100.00 |
CONT_ASSIGN | 208 | 1 | 1 | 100.00 |
CONT_ASSIGN | 211 | 1 | 1 | 100.00 |
ALWAYS | 218 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
77 |
1 |
1 |
78 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
83 |
1 |
1 |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
91 |
1 |
1 |
95 |
2 |
2 |
96 |
2 |
2 |
97 |
2 |
2 |
|
|
|
MISSING_ELSE |
101 |
1 |
1 |
102 |
1 |
1 |
103 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
109 |
1 |
1 |
|
|
|
MISSING_ELSE |
141 |
1 |
1 |
142 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
|
|
|
MISSING_ELSE |
149 |
1 |
1 |
150 |
1 |
1 |
154 |
1 |
1 |
204 |
1 |
1 |
208 |
1 |
1 |
211 |
1 |
1 |
218 |
1 |
1 |
220 |
1 |
1 |
223 |
1 |
1 |
Cond Coverage for Module :
tlul_adapter_reg
| Total | Covered | Percent |
Conditions | 49 | 47 | 95.92 |
Logical | 49 | 47 | 95.92 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 77
EXPRESSION (tl_i.a_valid & tl_o.a_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION (tl_o.d_valid & tl_i.d_ready)
------1----- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T6 |
1 | 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (a_ack & ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData)))
--1-- ----------------------------------2---------------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 80
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 80
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 80
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 81
EXPRESSION (a_ack & (tl_i.a_opcode == Get))
--1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 81
SUB-EXPRESSION (tl_i.a_opcode == Get)
-----------1----------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 83
EXPRESSION (wr_req & ((~err_internal)))
---1-- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T189,T190,T215 |
1 | 1 | Covered | T1,T2,T3 |
LINE 84
EXPRESSION (rd_req & ((~err_internal)))
---1-- --------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T189,T191,T215 |
1 | 1 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (rd_req ? AccessAckData : AccessAck)
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION ((error_i || err_internal || wr_req) ? '1 : rdata_i)
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 145
SUB-EXPRESSION (error_i || err_internal || wr_req)
---1--- ------2----- ---3--
-1- | -2- | -3- | Status | Tests |
0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 1 | Covered | T1,T2,T3 |
0 | 1 | 0 | Covered | T215,T216,T217 |
1 | 0 | 0 | Covered | T189,T190,T191 |
LINE 146
EXPRESSION (error_i || err_internal)
---1--- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T215,T216,T217 |
1 | 0 | Covered | T189,T190,T191 |
LINE 154
SUB-EXPRESSION (outstanding_q | (tl_i.a_valid & busy_i))
------1------ -----------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T189,T192,T190 |
1 | 0 | Covered | T1,T2,T3 |
LINE 154
SUB-EXPRESSION (tl_i.a_valid & busy_i)
------1----- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T218,T219,T220 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T6,T7,T8 |
LINE 208
EXPRESSION (addr_align_err | malformed_meta_err | tl_err | instr_error | intg_error)
-------1------ ---------2-------- ---3-- -----4----- -----5----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 1 | Unreachable | |
0 | 0 | 0 | 1 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | Covered | T2,T3,T27 |
0 | 1 | 0 | 0 | 0 | Not Covered | |
1 | 0 | 0 | 0 | 0 | Covered | T189,T190,T215 |
Branch Coverage for Module :
tlul_adapter_reg
| Line No. | Total | Covered | Percent |
Branches |
|
14 |
14 |
100.00 |
IF |
95 |
4 |
4 |
100.00 |
IF |
101 |
4 |
4 |
100.00 |
IF |
218 |
2 |
2 |
100.00 |
IF |
141 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv' or '../src/lowrisc_tlul_adapter_reg_0.1/rtl/tlul_adapter_reg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 95 if ((!rst_ni))
-2-: 96 if (a_ack)
-3-: 97 if (d_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 101 if ((!rst_ni))
-2-: 105 if (a_ack)
-3-: 109 (rd_req) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
1 |
Covered |
T1,T2,T3 |
0 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 218 if (wr_req)
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 141 if ((!rst_ni))
-2-: 144 if (a_ack)
-3-: 145 (((error_i || err_internal) || wr_req)) ?
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
1 |
Covered |
T1,T2,T3 |
0 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_adapter_reg
Assertion Details
AllowedLatency_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2862 |
2862 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
MatchedWidthAssert
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2862 |
2862 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T16 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |